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be2iscsi: Remove redundant MCC processing code
be_mcc_compl_process_isr is removed. MCC CQ processing is done only in beiscsi_process_mcc_cq and MCC CQE processing is done only in beiscsi_process_mcc_compl. Signed-off-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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2e4e8f6574
@ -328,76 +328,6 @@ static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
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return 0;
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}
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int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl)
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{
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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u16 compl_status, extd_status;
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struct be_dma_mem *tag_mem;
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unsigned int tag, wrb_idx;
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be_dws_le_to_cpu(compl, 4);
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tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK);
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wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT;
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if (!test_bit(MCC_TAG_STATE_RUNNING,
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&ctrl->ptag_state[tag].tag_state)) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX |
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BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
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"BC_%d : MBX cmd completed but not posted\n");
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return 0;
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}
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if (test_bit(MCC_TAG_STATE_TIMEOUT,
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&ctrl->ptag_state[tag].tag_state)) {
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beiscsi_log(phba, KERN_WARNING,
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BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
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BEISCSI_LOG_CONFIG,
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"BC_%d : MBX Completion for timeout Command from FW\n");
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/**
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* Check for the size before freeing resource.
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* Only for non-embedded cmd, PCI resource is allocated.
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**/
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tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
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if (tag_mem->size)
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pci_free_consistent(ctrl->pdev, tag_mem->size,
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tag_mem->va, tag_mem->dma);
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free_mcc_tag(ctrl, tag);
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return 0;
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}
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compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
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CQE_STATUS_COMPL_MASK;
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extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
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CQE_STATUS_EXTD_MASK;
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/* The ctrl.mcc_tag_status[tag] is filled with
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* [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
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* [7:0] = compl_status
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*/
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ctrl->mcc_tag_status[tag] = CQE_VALID_MASK;
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ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT);
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ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) &
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CQE_STATUS_ADDL_MASK;
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ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK);
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/* write ordering implied in wake_up_interruptible */
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clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state);
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wake_up_interruptible(&ctrl->mcc_wait[tag]);
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return 0;
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}
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static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
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{
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struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
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struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
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if (be_mcc_compl_is_new(compl)) {
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queue_tail_inc(mcc_cq);
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return compl;
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}
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return NULL;
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}
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/**
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* beiscsi_fail_session(): Closing session with appropriate error
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* @cls_session: ptr to session
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@ -528,27 +458,65 @@ void beiscsi_process_async_event(struct beiscsi_hba *phba,
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evt_code, compl->status, compl->flags);
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}
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int beiscsi_process_mcc(struct beiscsi_hba *phba)
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int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl)
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{
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struct be_mcc_compl *compl;
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int num = 0, status = 0;
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struct be_ctrl_info *ctrl = &phba->ctrl;
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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u16 compl_status, extd_status;
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struct be_dma_mem *tag_mem;
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unsigned int tag, wrb_idx;
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while ((compl = be_mcc_compl_get(phba))) {
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if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
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beiscsi_process_async_event(phba, compl);
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} else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
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status = be_mcc_compl_process(ctrl, compl);
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atomic_dec(&phba->ctrl.mcc_obj.q.used);
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}
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be_mcc_compl_use(compl);
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num++;
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/**
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* Just swap the status to host endian; mcc tag is opaquely copied
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* from mcc_wrb
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*/
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be_dws_le_to_cpu(compl, 4);
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tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK);
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wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT;
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if (!test_bit(MCC_TAG_STATE_RUNNING,
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&ctrl->ptag_state[tag].tag_state)) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX |
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BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
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"BC_%d : MBX cmd completed but not posted\n");
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return 0;
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}
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if (num)
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hwi_ring_cq_db(phba, phba->ctrl.mcc_obj.cq.id, num, 1);
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if (test_bit(MCC_TAG_STATE_TIMEOUT, &ctrl->ptag_state[tag].tag_state)) {
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beiscsi_log(phba, KERN_WARNING,
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BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
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BEISCSI_LOG_CONFIG,
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"BC_%d : MBX Completion for timeout Command from FW\n");
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/**
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* Check for the size before freeing resource.
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* Only for non-embedded cmd, PCI resource is allocated.
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**/
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tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
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if (tag_mem->size)
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pci_free_consistent(ctrl->pdev, tag_mem->size,
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tag_mem->va, tag_mem->dma);
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free_mcc_tag(ctrl, tag);
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return 0;
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}
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return status;
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compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
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CQE_STATUS_COMPL_MASK;
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extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
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CQE_STATUS_EXTD_MASK;
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/* The ctrl.mcc_tag_status[tag] is filled with
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* [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
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* [7:0] = compl_status
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*/
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ctrl->mcc_tag_status[tag] = CQE_VALID_MASK;
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ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT);
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ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) &
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CQE_STATUS_ADDL_MASK;
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ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK);
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/* write ordering forced in wake_up_interruptible */
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clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state);
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wake_up_interruptible(&ctrl->mcc_wait[tag]);
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return 0;
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}
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/*
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@ -562,16 +530,15 @@ int beiscsi_process_mcc(struct beiscsi_hba *phba)
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* Failure: Non-Zero
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*
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**/
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static int be_mcc_wait_compl(struct beiscsi_hba *phba)
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int be_mcc_compl_poll(struct beiscsi_hba *phba, unsigned int tag)
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{
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int i, status;
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int i;
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for (i = 0; i < mcc_timeout; i++) {
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if (beiscsi_error(phba))
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return -EIO;
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status = beiscsi_process_mcc(phba);
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if (status)
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return status;
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beiscsi_process_mcc_cq(phba);
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if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
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break;
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@ -588,22 +555,6 @@ static int be_mcc_wait_compl(struct beiscsi_hba *phba)
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return 0;
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}
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/*
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* be_mcc_notify_wait()- Notify and wait for Compl
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* @phba: driver private structure
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*
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* Notify MCC requests and wait for completion
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*
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* return
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* Success: 0
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* Failure: Non-Zero
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**/
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int be_mcc_notify_wait(struct beiscsi_hba *phba, unsigned int tag)
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{
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be_mcc_notify(phba, tag);
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return be_mcc_wait_compl(phba);
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}
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/*
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* be_mbox_db_ready_wait()- Check ready status
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* @ctrl: Function specific MBX data structure
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@ -741,13 +741,14 @@ int be_cmd_fw_uninit(struct be_ctrl_info *ctrl);
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struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem);
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struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba);
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int be_mcc_notify_wait(struct beiscsi_hba *phba, unsigned int tag);
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int be_mcc_compl_poll(struct beiscsi_hba *phba, unsigned int tag);
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void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag);
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unsigned int alloc_mcc_tag(struct beiscsi_hba *phba);
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void beiscsi_process_async_event(struct beiscsi_hba *phba,
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struct be_mcc_compl *compl);
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int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl);
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int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl);
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int be_mbox_notify(struct be_ctrl_info *ctrl);
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@ -2028,7 +2028,7 @@ static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
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phwi_ctrlr, cri_index));
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}
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static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
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void beiscsi_process_mcc_cq(struct beiscsi_hba *phba)
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{
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struct be_queue_info *mcc_cq;
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struct be_mcc_compl *mcc_compl;
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@ -2038,7 +2038,6 @@ static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
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mcc_compl = queue_tail_node(mcc_cq);
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mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
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while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
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if (num_processed >= 32) {
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hwi_ring_cq_db(phba, mcc_cq->id,
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num_processed, 0);
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@ -2047,7 +2046,7 @@ static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
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if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
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beiscsi_process_async_event(phba, mcc_compl);
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} else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
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be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
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beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl);
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atomic_dec(&phba->ctrl.mcc_obj.q.used);
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}
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@ -2060,7 +2059,6 @@ static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
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if (num_processed > 0)
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hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1);
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}
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/**
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@ -2269,7 +2267,7 @@ void beiscsi_process_all_cqs(struct work_struct *work)
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spin_lock_irqsave(&phba->isr_lock, flags);
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pbe_eq->todo_mcc_cq = false;
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spin_unlock_irqrestore(&phba->isr_lock, flags);
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beiscsi_process_mcc_isr(phba);
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beiscsi_process_mcc_cq(phba);
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}
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if (pbe_eq->todo_cq) {
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@ -853,6 +853,7 @@ void hwi_ring_cq_db(struct beiscsi_hba *phba,
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unsigned char rearm);
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unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
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void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
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static inline bool beiscsi_error(struct beiscsi_hba *phba)
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{
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@ -678,7 +678,8 @@ int mgmt_epfw_cleanup(struct beiscsi_hba *phba, unsigned short ulp_num)
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req->hdr_ring_id = cpu_to_le16(HWI_GET_DEF_HDRQ_ID(phba, ulp_num));
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req->data_ring_id = cpu_to_le16(HWI_GET_DEF_BUFQ_ID(phba, ulp_num));
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status = be_mcc_notify_wait(phba, tag);
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be_mcc_notify(phba, tag);
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status = be_mcc_compl_poll(phba, tag);
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if (status)
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beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
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"BG_%d : mgmt_epfw_cleanup , FAILED\n");
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