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ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15
When there is a cluster power down cycle in suspend, we need to set up the correct L2 RAM data RAM latency to make L2 cache work correctly. This is only needed for cluster 0 and needs to be done in tegra_resume before the cache is enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -45,6 +45,7 @@
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ENTRY(tegra_resume)
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check_cpu_part_num 0xc09, r8, r9
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bleq v7_invalidate_l1
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blne tegra_init_l2_for_a15
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cpu_id r0
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
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@ -68,6 +68,28 @@ ENDPROC(tegra_disable_clean_inv_dcache)
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#endif
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_init_l2_for_a15
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*
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* set up the correct L2 cache data RAM latency
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*/
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ENTRY(tegra_init_l2_for_a15)
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mrc p15, 0, r0, c0, c0, 5
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ubfx r0, r0, #8, #4
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tst r0, #1 @ only need for cluster 0
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bne _exit_init_l2_a15
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mrc p15, 0x1, r0, c9, c0, 2
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and r0, r0, #7
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cmp r0, #2
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bicne r0, r0, #7
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orrne r0, r0, #2
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mcrne p15, 0x1, r0, c9, c0, 2
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_exit_init_l2_a15:
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mov pc, lr
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ENDPROC(tegra_init_l2_for_a15)
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/*
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* tegra_sleep_cpu_finish(unsigned long v2p)
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*
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