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x86: consolidate spinlock.h
The cli and sti instructions need to be replaced by paravirt hooks. For the i386 architecture, this is already done. The code requirements aren't much different from x86_64 POV, so this part is consolidated in the common header Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Acked-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Glauber de Oliveira Costa
Ingo Molnar
parent
6abcd98ffa
commit
2fed0c507c
@ -1,5 +1,19 @@
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#ifndef _X86_SPINLOCK_H_
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#define _X86_SPINLOCK_H_
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define CLI_STRING "cli"
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#define STI_STRING "sti"
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#define CLI_STI_CLOBBERS
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#define CLI_STI_INPUT_ARGS
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#endif /* CONFIG_PARAVIRT */
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#ifdef CONFIG_X86_32
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# include "spinlock_32.h"
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#else
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# include "spinlock_64.h"
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#endif
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#endif
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@ -5,16 +5,6 @@
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#include <asm/rwlock.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <linux/compiler.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define CLI_STRING "cli"
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#define STI_STRING "sti"
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#define CLI_STI_CLOBBERS
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#define CLI_STI_INPUT_ARGS
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#endif /* CONFIG_PARAVIRT */
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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@ -27,23 +17,24 @@
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* (the type definitions are in asm/spinlock_types.h)
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*/
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static inline int __raw_spin_is_locked(raw_spinlock_t *x)
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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return *(volatile signed char *)(&(x)->slock) <= 0;
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return *(volatile signed char *)(&(lock)->slock) <= 0;
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}
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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asm volatile("\n1:\t"
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LOCK_PREFIX " ; decb %0\n\t"
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"jns 3f\n"
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"2:\t"
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"rep;nop\n\t"
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"cmpb $0,%0\n\t"
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"jle 2b\n\t"
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"jmp 1b\n"
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"3:\n\t"
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: "+m" (lock->slock) : : "memory");
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asm volatile(
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"\n1:\t"
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LOCK_PREFIX " ; decb %0\n\t"
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"jns 3f\n"
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"2:\t"
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"rep;nop\n\t"
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"cmpb $0,%0\n\t"
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"jle 2b\n\t"
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"jmp 1b\n"
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"3:\n\t"
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: "+m" (lock->slock) : : "memory");
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}
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/*
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@ -55,7 +46,8 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
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* irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use this variant.
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*/
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#ifndef CONFIG_PROVE_LOCKING
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static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
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static inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
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unsigned long flags)
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{
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asm volatile(
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"\n1:\t"
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@ -79,18 +71,20 @@ static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long fla
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"5:\n\t"
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: [slock] "+m" (lock->slock)
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: [flags] "r" (flags)
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CLI_STI_INPUT_ARGS
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CLI_STI_INPUT_ARGS
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: "memory" CLI_STI_CLOBBERS);
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}
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#endif
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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char oldval;
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signed char oldval;
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asm volatile(
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"xchgb %b0,%1"
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:"=q" (oldval), "+m" (lock->slock)
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:"0" (0) : "memory");
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return oldval > 0;
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}
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@ -112,7 +106,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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char oldval = 1;
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unsigned char oldval = 1;
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asm volatile("xchgb %b0, %1"
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: "=q" (oldval), "+m" (lock->slock)
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@ -139,31 +133,16 @@ static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*
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* The inline assembly is non-obvious. Think about it.
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*
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* Changed to use the same technique as rw semaphores. See
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* semaphore.h for details. -ben
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*
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* the helpers are in arch/i386/kernel/semaphore.c
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*/
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int __raw_read_can_lock(raw_rwlock_t *x)
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static inline int __raw_read_can_lock(raw_rwlock_t *lock)
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{
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return (int)(x)->lock > 0;
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return (int)(lock)->lock > 0;
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}
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int __raw_write_can_lock(raw_rwlock_t *x)
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static inline int __raw_write_can_lock(raw_rwlock_t *lock)
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{
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return (x)->lock == RW_LOCK_BIAS;
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return (lock)->lock == RW_LOCK_BIAS;
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}
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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@ -187,6 +166,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
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static inline int __raw_read_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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atomic_dec(count);
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if (atomic_read(count) >= 0)
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return 1;
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@ -197,6 +177,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *lock)
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static inline int __raw_write_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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@ -33,14 +33,21 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
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"cmpl $0,%0\n\t"
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"jle 3b\n\t"
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"jmp 1b\n"
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"2:\t" : "=m" (lock->slock) : : "memory");
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"2:\t"
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: "=m" (lock->slock) : : "memory");
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}
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/*
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* Same as __raw_spin_lock, but reenable interrupts during spinning.
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* It is easier for the lock validator if interrupts are not re-enabled
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* in the middle of a lock-acquire. This is a performance feature anyway
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* so we turn it off:
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*
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* NOTE: there's an irqs-on section here, which normally would have to be
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* irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use this variant.
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*/
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#ifndef CONFIG_PROVE_LOCKING
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static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
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static inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
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unsigned long flags)
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{
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asm volatile(
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"\n1:\t"
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@ -48,12 +55,12 @@ static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long fla
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"jns 5f\n"
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"testl $0x200, %1\n\t" /* interrupts were disabled? */
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"jz 4f\n\t"
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"sti\n"
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STI_STRING "\n"
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"3:\t"
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"rep;nop\n\t"
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"cmpl $0, %0\n\t"
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"jle 3b\n\t"
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"cli\n\t"
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CLI_STRING "\n\t"
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"jmp 1b\n"
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"4:\t"
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"rep;nop\n\t"
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@ -61,7 +68,9 @@ static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long fla
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"jg 1b\n\t"
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"jmp 4b\n"
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"5:\n\t"
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: "+m" (lock->slock) : "r" ((unsigned)flags) : "memory");
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: "+m" (lock->slock)
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: "r" ((unsigned)flags) CLI_STI_INPUT_ARGS
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: "memory" CLI_STI_CLOBBERS);
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}
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#endif
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@ -79,7 +88,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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asm volatile("movl $1,%0" :"=m" (lock->slock) :: "memory");
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asm volatile("movl $1,%0" : "=m" (lock->slock) :: "memory");
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}
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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@ -114,18 +123,18 @@ static inline int __raw_write_can_lock(raw_rwlock_t *lock)
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "subl $1,(%0)\n\t"
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asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
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"jns 1f\n"
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"call __read_lock_failed\n"
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"call __read_lock_failed\n\t"
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"1:\n"
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::"D" (rw), "i" (RW_LOCK_BIAS) : "memory");
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "subl %1,(%0)\n\t"
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asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
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"jz 1f\n"
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"\tcall __write_lock_failed\n\t"
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"call __write_lock_failed\n\t"
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"1:\n"
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::"D" (rw), "i" (RW_LOCK_BIAS) : "memory");
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}
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@ -133,6 +142,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
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static inline int __raw_read_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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atomic_dec(count);
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if (atomic_read(count) >= 0)
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return 1;
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@ -143,6 +153,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *lock)
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static inline int __raw_write_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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@ -151,12 +162,12 @@ static inline int __raw_write_trylock(raw_rwlock_t *lock)
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " ; incl %0" :"=m" (rw->lock) : : "memory");
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asm volatile(LOCK_PREFIX "incl %0" :"=m" (rw->lock) : : "memory");
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " ; addl $" RW_LOCK_BIAS_STR ",%0"
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asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ",%0"
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: "=m" (rw->lock) : : "memory");
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}
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