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ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI
Commit ca6e2ce086
is setting up few XCCR and
RCCR bits for I2S and DPS_A formats. Part of the bits are already set
for all formats and I believe that XDISABLE and RDISABLE bits are
format independent.
As XCCR and RCCR are found only from OMAP2430 and OMAP34xx, I move setup
of XDISABLE and RDISABLE to where those cpu's are tested and remove format
dependent part for simplicity.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
parent
9b30050908
commit
32080af7a6
@ -379,8 +379,8 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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regs->xcr2 |= XFIG;
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}
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if (cpu_is_omap2430() || cpu_is_omap34xx()) {
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regs->xccr = DXENDLY(1) | XDMAEN;
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regs->rccr = RFULL_CYCLE | RDMAEN;
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regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
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regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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@ -388,15 +388,11 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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/* 1-bit data delay */
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regs->rcr2 |= RDATDLY(1);
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regs->xcr2 |= XDATDLY(1);
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regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE;
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regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE);
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break;
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case SND_SOC_DAIFMT_DSP_A:
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/* 1-bit data delay */
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regs->rcr2 |= RDATDLY(1);
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regs->xcr2 |= XDATDLY(1);
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regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE;
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regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE);
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/* Invert FS polarity configuration */
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temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
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break;
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