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clk: add artpec-6 clock controller
Add a driver for the main clock controller of the Artpec-6 Soc. Signed-off-by: Lars Persson <larper@axis.com> [sboyd@codeaurora.org: Reformatted driver structure and of match] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Lars Persson
Stephen Boyd
parent
67bad3e5ce
commit
33b8ac917a
@ -973,7 +973,7 @@ S: Maintained
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L: linux-arm-kernel@axis.com
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F: arch/arm/mach-artpec
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F: arch/arm/boot/dts/artpec6*
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F: drivers/clk/clk-artpec6.c
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F: drivers/clk/axis
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ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
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M: Nicolas Ferre <nicolas.ferre@atmel.com>
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@ -51,6 +51,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
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obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
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obj-$(CONFIG_COMMON_CLK_AT91) += at91/
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obj-$(CONFIG_ARCH_ARTPEC) += axis/
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obj-y += bcm/
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obj-$(CONFIG_ARCH_BERLIN) += berlin/
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obj-$(CONFIG_ARCH_HISI) += hisilicon/
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1
drivers/clk/axis/Makefile
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1
drivers/clk/axis/Makefile
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@ -0,0 +1 @@
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obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
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242
drivers/clk/axis/clk-artpec6.c
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242
drivers/clk/axis/clk-artpec6.c
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@ -0,0 +1,242 @@
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/*
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* ARTPEC-6 clock initialization
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*
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* Copyright 2015-2016 Axis Comunications AB.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
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#define NUM_I2S_CLOCKS 2
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struct artpec6_clkctrl_drvdata {
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struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
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void __iomem *syscon_base;
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struct clk_onecell_data clk_data;
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spinlock_t i2scfg_lock;
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};
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static struct artpec6_clkctrl_drvdata *clkdata;
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static const char *const i2s_clk_names[NUM_I2S_CLOCKS] = {
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"i2s0",
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"i2s1",
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};
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static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
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ARTPEC6_CLK_I2S0_CLK,
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ARTPEC6_CLK_I2S1_CLK,
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};
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static void of_artpec6_clkctrl_setup(struct device_node *np)
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{
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int i;
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const char *sys_refclk_name;
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u32 pll_mode, pll_m, pll_n;
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struct clk **clks;
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/* Mandatory parent clock. */
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i = of_property_match_string(np, "clock-names", "sys_refclk");
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if (i < 0)
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return;
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sys_refclk_name = of_clk_get_parent_name(np, i);
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clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
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if (!clkdata)
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return;
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clks = clkdata->clk_table;
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for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
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clks[i] = ERR_PTR(-EPROBE_DEFER);
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clkdata->syscon_base = of_iomap(np, 0);
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BUG_ON(clkdata->syscon_base == NULL);
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/* Read PLL1 factors configured by boot strap pins. */
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pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
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switch (pll_mode) {
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case 0: /* DDR3-2133 mode */
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pll_m = 4;
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pll_n = 85;
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break;
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case 1: /* DDR3-1866 mode */
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pll_m = 6;
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pll_n = 112;
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break;
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case 2: /* DDR3-1600 mode */
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pll_m = 4;
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pll_n = 64;
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break;
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case 3: /* DDR3-1333 mode */
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pll_m = 8;
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pll_n = 106;
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break;
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}
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clks[ARTPEC6_CLK_CPU] =
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clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
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pll_m);
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clks[ARTPEC6_CLK_CPU_PERIPH] =
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clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
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/* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
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clks[ARTPEC6_CLK_UART_PCLK] =
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clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
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clks[ARTPEC6_CLK_UART_REFCLK] =
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clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
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50000000);
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clks[ARTPEC6_CLK_SPI_PCLK] =
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clk_register_fixed_factor(NULL, "spi_pclk", "cpu", 0, 1, 8);
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clks[ARTPEC6_CLK_SPI_SSPCLK] =
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clk_register_fixed_rate(NULL, "spi_sspclk", sys_refclk_name, 0,
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50000000);
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clks[ARTPEC6_CLK_DBG_PCLK] =
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clk_register_fixed_factor(NULL, "dbg_pclk", "cpu", 0, 1, 8);
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clkdata->clk_data.clks = clkdata->clk_table;
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clkdata->clk_data.clk_num = ARTPEC6_CLK_NUMCLOCKS;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clkdata->clk_data);
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}
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CLK_OF_DECLARE(artpec6_clkctrl, "axis,artpec6-clkctrl",
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of_artpec6_clkctrl_setup);
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static int artpec6_clkctrl_probe(struct platform_device *pdev)
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{
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int propidx;
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct clk **clks = clkdata->clk_table;
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const char *sys_refclk_name;
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const char *i2s_refclk_name = NULL;
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const char *frac_clk_name[2] = { NULL, NULL };
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const char *i2s_mux_parents[2];
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u32 muxreg;
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int i;
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int err = 0;
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/* Mandatory parent clock. */
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propidx = of_property_match_string(np, "clock-names", "sys_refclk");
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if (propidx < 0)
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return -EINVAL;
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sys_refclk_name = of_clk_get_parent_name(np, propidx);
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/* Find clock names of optional parent clocks. */
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propidx = of_property_match_string(np, "clock-names", "i2s_refclk");
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if (propidx >= 0)
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i2s_refclk_name = of_clk_get_parent_name(np, propidx);
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propidx = of_property_match_string(np, "clock-names", "frac_clk0");
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if (propidx >= 0)
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frac_clk_name[0] = of_clk_get_parent_name(np, propidx);
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propidx = of_property_match_string(np, "clock-names", "frac_clk1");
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if (propidx >= 0)
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frac_clk_name[1] = of_clk_get_parent_name(np, propidx);
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spin_lock_init(&clkdata->i2scfg_lock);
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clks[ARTPEC6_CLK_NAND_CLKA] =
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clk_register_fixed_factor(dev, "nand_clka", "cpu", 0, 1, 8);
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clks[ARTPEC6_CLK_NAND_CLKB] =
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clk_register_fixed_rate(dev, "nand_clkb", sys_refclk_name, 0,
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100000000);
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clks[ARTPEC6_CLK_ETH_ACLK] =
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clk_register_fixed_factor(dev, "eth_aclk", "cpu", 0, 1, 4);
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clks[ARTPEC6_CLK_DMA_ACLK] =
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clk_register_fixed_factor(dev, "dma_aclk", "cpu", 0, 1, 4);
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clks[ARTPEC6_CLK_PTP_REF] =
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clk_register_fixed_rate(dev, "ptp_ref", sys_refclk_name, 0,
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100000000);
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clks[ARTPEC6_CLK_SD_PCLK] =
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clk_register_fixed_rate(dev, "sd_pclk", sys_refclk_name, 0,
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100000000);
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clks[ARTPEC6_CLK_SD_IMCLK] =
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clk_register_fixed_rate(dev, "sd_imclk", sys_refclk_name, 0,
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100000000);
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clks[ARTPEC6_CLK_I2S_HST] =
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clk_register_fixed_factor(dev, "i2s_hst", "cpu", 0, 1, 8);
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for (i = 0; i < NUM_I2S_CLOCKS; ++i) {
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if (i2s_refclk_name && frac_clk_name[i]) {
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i2s_mux_parents[0] = frac_clk_name[i];
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i2s_mux_parents[1] = i2s_refclk_name;
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clks[i2s_clk_indexes[i]] =
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clk_register_mux(dev, i2s_clk_names[i],
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i2s_mux_parents, 2,
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CLK_SET_RATE_NO_REPARENT |
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CLK_SET_RATE_PARENT,
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clkdata->syscon_base + 0x14, i, 1,
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0, &clkdata->i2scfg_lock);
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} else if (frac_clk_name[i]) {
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/* Lock the mux for internal clock reference. */
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muxreg = readl(clkdata->syscon_base + 0x14);
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muxreg &= ~BIT(i);
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writel(muxreg, clkdata->syscon_base + 0x14);
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clks[i2s_clk_indexes[i]] =
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clk_register_fixed_factor(dev, i2s_clk_names[i],
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frac_clk_name[i], 0, 1,
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1);
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} else if (i2s_refclk_name) {
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/* Lock the mux for external clock reference. */
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muxreg = readl(clkdata->syscon_base + 0x14);
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muxreg |= BIT(i);
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writel(muxreg, clkdata->syscon_base + 0x14);
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clks[i2s_clk_indexes[i]] =
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clk_register_fixed_factor(dev, i2s_clk_names[i],
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i2s_refclk_name, 0, 1, 1);
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}
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}
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clks[ARTPEC6_CLK_I2C] =
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clk_register_fixed_rate(dev, "i2c", sys_refclk_name, 0, 100000000);
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clks[ARTPEC6_CLK_SYS_TIMER] =
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clk_register_fixed_rate(dev, "timer", sys_refclk_name, 0,
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100000000);
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clks[ARTPEC6_CLK_FRACDIV_IN] =
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clk_register_fixed_rate(dev, "fracdiv_in", sys_refclk_name, 0,
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600000000);
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for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i) {
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if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER) {
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dev_err(dev,
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"Failed to register clock at index %d err=%ld\n",
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i, PTR_ERR(clks[i]));
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err = PTR_ERR(clks[i]);
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}
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}
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return err;
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}
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static const struct of_device_id artpec_clkctrl_of_match[] = {
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{ .compatible = "axis,artpec6-clkctrl" },
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{}
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};
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static struct platform_driver artpec6_clkctrl_driver = {
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.probe = artpec6_clkctrl_probe,
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.driver = {
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.name = "artpec6_clkctrl",
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.of_match_table = artpec_clkctrl_of_match,
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},
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};
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builtin_platform_driver(artpec6_clkctrl_driver);
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