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clk: socfpga: Add a second parent option for the dbg_base_clk

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The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Dinh Nguyen 2015-07-24 22:30:18 -05:00 committed by Michael Turquette
parent 0f350f063e
commit 34d5003bfb
2 changed files with 15 additions and 4 deletions
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18
drivers/clk/socfpga/clk-periph.c
View File

@ -44,8 +44,17 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
return parent_rate / div;
}
static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
{
u32 clk_src;
clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
return clk_src & 0x1;
}
static const struct clk_ops periclk_ops = {
.recalc_rate = clk_periclk_recalc_rate,
.get_parent = clk_periclk_get_parent,
};
static __init void __socfpga_periph_init(struct device_node *node,
@ -55,7 +64,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
@ -89,9 +98,10 @@ static __init void __socfpga_periph_init(struct device_node *node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
parent_name = of_clk_get_parent_name(node, 0);
init.parent_names = &parent_name;
init.num_parents = 1;
init.num_parents = of_clk_parent_fill(node, parent_name,
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
periph_clk->hw.hw.init = &init;

1
drivers/clk/socfpga/clk.h
View File

@ -22,6 +22,7 @@
/* Clock Manager offsets */
#define CLKMGR_CTRL 0x0
#define CLKMGR_BYPASS 0x4
#define CLKMGR_DBCTRL 0x10
#define CLKMGR_L4SRC 0x70
#define CLKMGR_PERPLL_SRC 0xAC