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[MTD] [NAND] sh_flctl: fix compile error
Fix compile error because the first patch was broken -- the file got truncated. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Yoshihiro Shimoda
David Woodhouse
parent
be8f78b8e8
commit
35a347991c
@ -299,3 +299,580 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
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break;
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case NAND_CMD_PAGEPROG:
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addr_len_bytes = flctl->rw_ADRCNT;
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flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
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break;
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case NAND_CMD_READID:
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flcmncr_val &= ~SNAND_E;
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addr_len_bytes = ADRCNT_1;
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break;
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case NAND_CMD_STATUS:
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case NAND_CMD_RESET:
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flcmncr_val &= ~SNAND_E;
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flcmdcr_val &= ~(DOADR_E | DOSR_E);
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break;
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default:
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break;
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}
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/* Set address bytes parameter */
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flcmdcr_val |= addr_len_bytes;
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/* Now actually write */
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writel(flcmncr_val, FLCMNCR(flctl));
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writel(flcmdcr_val, FLCMDCR(flctl));
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writel(flcmcdr_val, FLCMCDR(flctl));
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}
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static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf)
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{
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
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chip->read_buf(mtd, p, eccsize);
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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if (flctl->hwecc_cant_correct[i])
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += 0;
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}
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return 0;
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}
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static void flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf)
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{
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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const uint8_t *p = buf;
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
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chip->write_buf(mtd, p, eccsize);
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}
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static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int sector, page_sectors;
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if (flctl->page_size)
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page_sectors = 4;
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else
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page_sectors = 1;
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writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
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FLCMNCR(flctl));
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set_cmd_regs(mtd, NAND_CMD_READ0,
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(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
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for (sector = 0; sector < page_sectors; sector++) {
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int ret;
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empty_fifo(flctl);
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writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl));
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writel(page_addr << 2 | sector, FLADR(flctl));
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start_translation(flctl);
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read_fiforeg(flctl, 512, 512 * sector);
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ret = read_ecfiforeg(flctl,
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&flctl->done_buff[mtd->writesize + 16 * sector]);
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if (ret)
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flctl->hwecc_cant_correct[sector] = 1;
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writel(0x0, FL4ECCCR(flctl));
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wait_completion(flctl);
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}
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writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
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FLCMNCR(flctl));
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}
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static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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set_cmd_regs(mtd, NAND_CMD_READ0,
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(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
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empty_fifo(flctl);
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if (flctl->page_size) {
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int i;
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/* In case that the page size is 2k */
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for (i = 0; i < 16 * 3; i++)
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flctl->done_buff[i] = 0xFF;
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set_addr(mtd, 3 * 528 + 512, page_addr);
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writel(16, FLDTCNTR(flctl));
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start_translation(flctl);
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read_fiforeg(flctl, 16, 16 * 3);
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wait_completion(flctl);
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} else {
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/* In case that the page size is 512b */
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set_addr(mtd, 512, page_addr);
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writel(16, FLDTCNTR(flctl));
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start_translation(flctl);
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read_fiforeg(flctl, 16, 0);
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wait_completion(flctl);
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}
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}
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static void execmd_write_page_sector(struct mtd_info *mtd)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int i, page_addr = flctl->seqin_page_addr;
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int sector, page_sectors;
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if (flctl->page_size)
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page_sectors = 4;
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else
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page_sectors = 1;
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writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
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set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
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(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
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for (sector = 0; sector < page_sectors; sector++) {
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empty_fifo(flctl);
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writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl));
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writel(page_addr << 2 | sector, FLADR(flctl));
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start_translation(flctl);
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write_fiforeg(flctl, 512, 512 * sector);
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for (i = 0; i < 4; i++) {
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wait_wecfifo_ready(flctl); /* wait for write ready */
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writel(0xFFFFFFFF, FLECFIFO(flctl));
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}
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wait_completion(flctl);
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}
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writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
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}
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static void execmd_write_oob(struct mtd_info *mtd)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int page_addr = flctl->seqin_page_addr;
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int sector, page_sectors;
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if (flctl->page_size) {
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sector = 3;
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page_sectors = 4;
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} else {
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sector = 0;
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page_sectors = 1;
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}
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set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
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(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
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for (; sector < page_sectors; sector++) {
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empty_fifo(flctl);
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set_addr(mtd, sector * 528 + 512, page_addr);
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writel(16, FLDTCNTR(flctl)); /* set read size */
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start_translation(flctl);
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write_fiforeg(flctl, 16, 16 * sector);
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wait_completion(flctl);
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}
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}
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static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
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int column, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t read_cmd = 0;
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flctl->read_bytes = 0;
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if (command != NAND_CMD_PAGEPROG)
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flctl->index = 0;
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switch (command) {
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case NAND_CMD_READ1:
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case NAND_CMD_READ0:
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if (flctl->hwecc) {
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/* read page with hwecc */
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execmd_read_page_sector(mtd, page_addr);
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break;
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}
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empty_fifo(flctl);
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if (flctl->page_size)
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set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
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else
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set_cmd_regs(mtd, command, command);
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set_addr(mtd, 0, page_addr);
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flctl->read_bytes = mtd->writesize + mtd->oobsize;
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flctl->index += column;
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goto read_normal_exit;
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case NAND_CMD_READOOB:
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if (flctl->hwecc) {
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/* read page with hwecc */
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execmd_read_oob(mtd, page_addr);
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break;
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}
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empty_fifo(flctl);
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if (flctl->page_size) {
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set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
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set_addr(mtd, mtd->writesize, page_addr);
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} else {
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set_cmd_regs(mtd, command, command);
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set_addr(mtd, 0, page_addr);
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}
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flctl->read_bytes = mtd->oobsize;
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goto read_normal_exit;
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case NAND_CMD_READID:
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empty_fifo(flctl);
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set_cmd_regs(mtd, command, command);
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set_addr(mtd, 0, 0);
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flctl->read_bytes = 4;
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writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
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start_translation(flctl);
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read_datareg(flctl, 0); /* read and end */
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break;
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case NAND_CMD_ERASE1:
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flctl->erase1_page_addr = page_addr;
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break;
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case NAND_CMD_ERASE2:
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set_cmd_regs(mtd, NAND_CMD_ERASE1,
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(command << 8) | NAND_CMD_ERASE1);
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set_addr(mtd, -1, flctl->erase1_page_addr);
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start_translation(flctl);
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wait_completion(flctl);
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break;
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case NAND_CMD_SEQIN:
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if (!flctl->page_size) {
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/* output read command */
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if (column >= mtd->writesize) {
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column -= mtd->writesize;
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read_cmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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read_cmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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read_cmd = NAND_CMD_READ1;
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}
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}
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flctl->seqin_column = column;
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flctl->seqin_page_addr = page_addr;
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flctl->seqin_read_cmd = read_cmd;
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break;
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case NAND_CMD_PAGEPROG:
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empty_fifo(flctl);
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if (!flctl->page_size) {
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set_cmd_regs(mtd, NAND_CMD_SEQIN,
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flctl->seqin_read_cmd);
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set_addr(mtd, -1, -1);
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writel(0, FLDTCNTR(flctl)); /* set 0 size */
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start_translation(flctl);
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wait_completion(flctl);
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}
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if (flctl->hwecc) {
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/* write page with hwecc */
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if (flctl->seqin_column == mtd->writesize)
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execmd_write_oob(mtd);
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else if (!flctl->seqin_column)
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execmd_write_page_sector(mtd);
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else
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printk(KERN_ERR "Invalid address !?\n");
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break;
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}
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set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
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set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
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writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
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start_translation(flctl);
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write_fiforeg(flctl, flctl->index, 0);
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wait_completion(flctl);
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break;
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case NAND_CMD_STATUS:
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set_cmd_regs(mtd, command, command);
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set_addr(mtd, -1, -1);
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flctl->read_bytes = 1;
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writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
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start_translation(flctl);
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read_datareg(flctl, 0); /* read and end */
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break;
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case NAND_CMD_RESET:
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set_cmd_regs(mtd, command, command);
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set_addr(mtd, -1, -1);
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writel(0, FLDTCNTR(flctl)); /* set 0 size */
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start_translation(flctl);
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wait_completion(flctl);
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break;
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default:
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break;
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}
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return;
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read_normal_exit:
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writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
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start_translation(flctl);
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read_fiforeg(flctl, flctl->read_bytes, 0);
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wait_completion(flctl);
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return;
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}
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static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t flcmncr_val = readl(FLCMNCR(flctl));
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switch (chipnr) {
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case -1:
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flcmncr_val &= ~CE0_ENABLE;
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writel(flcmncr_val, FLCMNCR(flctl));
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break;
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case 0:
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flcmncr_val |= CE0_ENABLE;
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writel(flcmncr_val, FLCMNCR(flctl));
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break;
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default:
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BUG();
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}
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}
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static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int i, index = flctl->index;
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for (i = 0; i < len; i++)
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flctl->done_buff[index + i] = buf[i];
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flctl->index += len;
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}
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static uint8_t flctl_read_byte(struct mtd_info *mtd)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int index = flctl->index;
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uint8_t data;
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data = flctl->done_buff[index];
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flctl->index++;
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return data;
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}
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static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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buf[i] = flctl_read_byte(mtd);
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}
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static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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if (buf[i] != flctl_read_byte(mtd))
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return -EFAULT;
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return 0;
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}
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static void flctl_register_init(struct sh_flctl *flctl, unsigned long val)
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{
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writel(val, FLCMNCR(flctl));
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}
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static int flctl_chip_init_tail(struct mtd_info *mtd)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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struct nand_chip *chip = &flctl->chip;
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if (mtd->writesize == 512) {
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flctl->page_size = 0;
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if (chip->chipsize > (32 << 20)) {
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/* big than 32MB */
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flctl->rw_ADRCNT = ADRCNT_4;
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flctl->erase_ADRCNT = ADRCNT_3;
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} else if (chip->chipsize > (2 << 16)) {
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/* big than 128KB */
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flctl->rw_ADRCNT = ADRCNT_3;
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flctl->erase_ADRCNT = ADRCNT_2;
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} else {
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flctl->rw_ADRCNT = ADRCNT_2;
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flctl->erase_ADRCNT = ADRCNT_1;
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}
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} else {
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flctl->page_size = 1;
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if (chip->chipsize > (128 << 20)) {
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/* big than 128MB */
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flctl->rw_ADRCNT = ADRCNT2_E;
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flctl->erase_ADRCNT = ADRCNT_3;
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} else if (chip->chipsize > (8 << 16)) {
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/* big than 512KB */
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flctl->rw_ADRCNT = ADRCNT_4;
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flctl->erase_ADRCNT = ADRCNT_2;
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} else {
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flctl->rw_ADRCNT = ADRCNT_3;
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flctl->erase_ADRCNT = ADRCNT_1;
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}
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}
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if (flctl->hwecc) {
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if (mtd->writesize == 512) {
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chip->ecc.layout = &flctl_4secc_oob_16;
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chip->badblock_pattern = &flctl_4secc_smallpage;
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} else {
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chip->ecc.layout = &flctl_4secc_oob_64;
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chip->badblock_pattern = &flctl_4secc_largepage;
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}
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chip->ecc.size = 512;
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chip->ecc.bytes = 10;
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chip->ecc.read_page = flctl_read_page_hwecc;
|
||||
chip->ecc.write_page = flctl_write_page_hwecc;
|
||||
chip->ecc.mode = NAND_ECC_HW;
|
||||
|
||||
/* 4 symbols ECC enabled */
|
||||
writel(readl(FLCMNCR(flctl)) | _4ECCEN | ECCPOS2 | ECCPOS_02,
|
||||
FLCMNCR(flctl));
|
||||
} else {
|
||||
chip->ecc.mode = NAND_ECC_SOFT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init flctl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct sh_flctl *flctl;
|
||||
struct mtd_info *flctl_mtd;
|
||||
struct nand_chip *nand;
|
||||
struct sh_flctl_platform_data *pdata;
|
||||
int ret;
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (pdata == NULL) {
|
||||
printk(KERN_ERR "sh_flctl platform_data not found.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL);
|
||||
if (!flctl) {
|
||||
printk(KERN_ERR "Unable to allocate NAND MTD dev structure.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
printk(KERN_ERR "%s: resource not found.\n", __func__);
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
|
||||
flctl->reg = ioremap(res->start, res->end - res->start + 1);
|
||||
if (flctl->reg == NULL) {
|
||||
printk(KERN_ERR "%s: ioremap error.\n", __func__);
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, flctl);
|
||||
flctl_mtd = &flctl->mtd;
|
||||
nand = &flctl->chip;
|
||||
flctl_mtd->priv = nand;
|
||||
flctl->hwecc = pdata->has_hwecc;
|
||||
|
||||
flctl_register_init(flctl, pdata->flcmncr_val);
|
||||
|
||||
nand->options = NAND_NO_AUTOINCR;
|
||||
|
||||
/* Set address of hardware control function */
|
||||
/* 20 us command delay time */
|
||||
nand->chip_delay = 20;
|
||||
|
||||
nand->read_byte = flctl_read_byte;
|
||||
nand->write_buf = flctl_write_buf;
|
||||
nand->read_buf = flctl_read_buf;
|
||||
nand->verify_buf = flctl_verify_buf;
|
||||
nand->select_chip = flctl_select_chip;
|
||||
nand->cmdfunc = flctl_cmdfunc;
|
||||
|
||||
ret = nand_scan_ident(flctl_mtd, 1);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = flctl_chip_init_tail(flctl_mtd);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = nand_scan_tail(flctl_mtd);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
add_mtd_partitions(flctl_mtd, pdata->parts, pdata->nr_parts);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
kfree(flctl);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __exit flctl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_flctl *flctl = platform_get_drvdata(pdev);
|
||||
|
||||
nand_release(&flctl->mtd);
|
||||
kfree(flctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver flctl_driver = {
|
||||
.probe = flctl_probe,
|
||||
.remove = flctl_remove,
|
||||
.driver = {
|
||||
.name = "sh_flctl",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init flctl_nand_init(void)
|
||||
{
|
||||
return platform_driver_register(&flctl_driver);
|
||||
}
|
||||
|
||||
static void __exit flctl_nand_cleanup(void)
|
||||
{
|
||||
platform_driver_unregister(&flctl_driver);
|
||||
}
|
||||
|
||||
module_init(flctl_nand_init);
|
||||
module_exit(flctl_nand_cleanup);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Yoshihiro Shimoda");
|
||||
MODULE_DESCRIPTION("SuperH FLCTL driver");
|
||||
MODULE_ALIAS("platform:sh_flctl");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user