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PCI: mvebu: Disable prefetchable memory support in PCI-to-PCI bridge

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The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able
to dynamically set up MBus address decoding windows for PCI I/O and
memory regions depending on the PCI devices enumerated by Linux.

However, this emulated PCI-to-PCI bridge logic makes the Linux PCI
core believe that prefetchable memory regions are supported (because
the registers are read/write), while in fact no adress decoding window
is ever created for such regions. Since the Marvell MBus address
decoding windows do not distinguish memory regions and prefetchable
memory regions, this patch takes a simple approach: change the
PCI-to-PCI bridge emulation to let the Linux PCI core know that we
don't support prefetchable memory regions.

To achieve this, we simply make the prefetchable memory base a
read-only register that always returns 0. Reading/writing all the
other prefetchable memory related registers has no effect.

This problem was originally reported by Finn Hoffmann
<finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working
on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem
was that the PCI-to-PCI bridge emulation was making the Linux PCI core
believe that we support prefetchable memory, so the Linux PCI core was
only filling the prefetchable memory base and limit registers, which
does not lead to a MBus window being created. The below patch has been
confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has
otherwise been successfully tested on the Armada XP GP platform with a
e1000e PCIe NIC and a Marvell SATA PCIe card.

Reported-by: Finn Hoffmann <finn@uni-bremen.de>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Thomas Petazzoni 2013-08-01 15:44:19 +02:00 committed by Bjorn Helgaas
parent aa914f5ec2
commit 36dd1f3e02
1 changed files with 1 additions and 26 deletions
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27
drivers/pci/host/pci-mvebu.c
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@ -86,10 +86,6 @@ struct mvebu_sw_pci_bridge {
u16 secondary_status;
u16 membase;
u16 memlimit;
u16 prefmembase;
u16 prefmemlimit;
u32 prefbaseupper;
u32 preflimitupper;
u16 iobaseupper;
u16 iolimitupper;
u8 cappointer;
@ -419,15 +415,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
break;
case PCI_PREF_MEMORY_BASE:
*value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
break;
case PCI_PREF_BASE_UPPER32:
*value = bridge->prefbaseupper;
break;
case PCI_PREF_LIMIT_UPPER32:
*value = bridge->preflimitupper;
*value = 0;
break;
case PCI_IO_BASE_UPPER16:
@ -501,19 +489,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
mvebu_pcie_handle_membase_change(port);
break;
case PCI_PREF_MEMORY_BASE:
bridge->prefmembase = value & 0xffff;
bridge->prefmemlimit = value >> 16;
break;
case PCI_PREF_BASE_UPPER32:
bridge->prefbaseupper = value;
break;
case PCI_PREF_LIMIT_UPPER32:
bridge->preflimitupper = value;
break;
case PCI_IO_BASE_UPPER16:
bridge->iobaseupper = value & 0xffff;
bridge->iolimitupper = value >> 16;