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Merge tag 'mvebu-soc-3.16-2' of git://git.infradead.org/linux-mvebu into next/soc
Merge "mvebu SoC changes for v3.16 (incremental #2)" from Jason Cooper <jason@lakedaemon.net>: - mvebu - fix coherency on big-endian in -next - hardware IO coherency - L2/PCIe deadlock workaround - small coherency cleanups * tag 'mvebu-soc-3.16-2' of git://git.infradead.org/linux-mvebu: ARM: mvebu: returns ll_get_cpuid() to ll_get_coherency_cpumask() ARM: mvebu: improve comments in coherency_ll.S ARM: mvebu: fix indentation of assembly instructions in coherency_ll.S ARM: mvebu: fix big endian booting after coherency code rework ARM: mvebu: coherency: fix registration of PCI bus notifier when !PCI ARM: mvebu: implement L2/PCIe deadlock workaround ARM: mvebu: use hardware I/O coherency also for PCI devices Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
37f5f4e173
@ -29,8 +29,10 @@
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#include <linux/slab.h>
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#include <linux/mbus.h>
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#include <linux/clk.h>
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#include <linux/pci.h>
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#include <asm/smp_plat.h>
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#include <asm/cacheflush.h>
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#include <asm/mach/map.h>
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#include "armada-370-xp.h"
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#include "coherency.h"
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#include "mvebu-soc-id.h"
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@ -274,8 +276,8 @@ static struct dma_map_ops mvebu_hwcc_dma_ops = {
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.set_dma_mask = arm_dma_set_mask,
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};
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static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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static int mvebu_hwcc_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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{
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struct device *dev = __dev;
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@ -286,8 +288,8 @@ static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
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return NOTIFY_OK;
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}
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static struct notifier_block mvebu_hwcc_platform_nb = {
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.notifier_call = mvebu_hwcc_platform_notifier,
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static struct notifier_block mvebu_hwcc_nb = {
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.notifier_call = mvebu_hwcc_notifier,
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};
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static void __init armada_370_coherency_init(struct device_node *np)
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@ -308,9 +310,47 @@ static void __init armada_370_coherency_init(struct device_node *np)
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set_cpu_coherent();
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}
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/*
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* This ioremap hook is used on Armada 375/38x to ensure that PCIe
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* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
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* is needed as a workaround for a deadlock issue between the PCIe
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* interface and the cache controller.
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*/
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static void __iomem *
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armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
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unsigned int mtype, void *caller)
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{
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struct resource pcie_mem;
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mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
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if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
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mtype = MT_UNCACHED;
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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}
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static void __init armada_375_380_coherency_init(struct device_node *np)
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{
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struct device_node *cache_dn;
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coherency_cpu_base = of_iomap(np, 0);
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arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
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/*
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* Add the PL310 property "arm,io-coherent". This makes sure the
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* outer sync operation is not used, which allows to
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* workaround the system erratum that causes deadlocks when
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* doing PCIe in an SMP situation on Armada 375 and Armada
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* 38x.
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*/
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for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
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struct property *p;
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
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of_add_property(cache_dn, p);
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}
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}
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static int coherency_type(void)
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@ -375,9 +415,21 @@ static int __init coherency_late_init(void)
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}
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bus_register_notifier(&platform_bus_type,
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&mvebu_hwcc_platform_nb);
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&mvebu_hwcc_nb);
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return 0;
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}
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postcore_initcall(coherency_late_init);
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#if IS_ENABLED(CONFIG_PCI)
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static int __init coherency_pci_init(void)
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{
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if (coherency_available())
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bus_register_notifier(&pci_bus_type,
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&mvebu_hwcc_nb);
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return 0;
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}
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arch_initcall(coherency_pci_init);
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#endif
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@ -24,52 +24,69 @@
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#include <asm/cp15.h>
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.text
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/* Returns with the coherency address in r1 (r0 is untouched)*/
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/* Returns the coherency base address in r1 (r0 is untouched) */
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ENTRY(ll_get_coherency_base)
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mrc p15, 0, r1, c1, c0, 0
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tst r1, #CR_M @ Check MMU bit enabled
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bne 1f
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/* use physical address of the coherency register */
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/*
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* MMU is disabled, use the physical address of the coherency
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* base address.
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*/
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adr r1, 3f
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ldr r3, [r1]
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ldr r1, [r1, r3]
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b 2f
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1:
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/* use virtual address of the coherency register */
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/*
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* MMU is enabled, use the virtual address of the coherency
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* base address.
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*/
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ldr r1, =coherency_base
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ldr r1, [r1]
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2:
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mov pc, lr
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ENDPROC(ll_get_coherency_base)
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/* Returns with the CPU ID in r3 (r0 is untouched)*/
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ENTRY(ll_get_cpuid)
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/*
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* Returns the coherency CPU mask in r3 (r0 is untouched). This
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* coherency CPU mask can be used with the coherency fabric
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* configuration and control registers. Note that the mask is already
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* endian-swapped as appropriate so that the calling functions do not
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* have to care about endianness issues while accessing the coherency
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* fabric registers
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*/
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ENTRY(ll_get_coherency_cpumask)
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mrc 15, 0, r3, cr0, cr0, 5
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and r3, r3, #15
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mov r2, #(1 << 24)
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lsl r3, r2, r3
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ARM_BE8(rev r1, r1)
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ARM_BE8(rev r3, r3)
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mov pc, lr
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ENDPROC(ll_get_cpuid)
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ENDPROC(ll_get_coherency_cpumask)
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/* ll_add_cpu_to_smp_group, ll_enable_coherency and
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* ll_disable_coherency use strex/ldrex whereas MMU can be off. The
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* Armada XP SoC has an exclusive monitor that can track transactions
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* to Device and/or SO and as such also when MMU is disabled the
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* exclusive transactions will be functional
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/*
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* ll_add_cpu_to_smp_group(), ll_enable_coherency() and
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* ll_disable_coherency() use the strex/ldrex instructions while the
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* MMU can be disabled. The Armada XP SoC has an exclusive monitor
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* that tracks transactions to Device and/or SO memory and thanks to
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* that, exclusive transactions are functional even when the MMU is
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* disabled.
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*/
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ENTRY(ll_add_cpu_to_smp_group)
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/*
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* r0 being untouched in ll_get_coherency_base and
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* ll_get_cpuid, we can use it to save lr modifing it with the
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* following bl
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* As r0 is not modified by ll_get_coherency_base() and
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* ll_get_coherency_cpumask(), we use it to temporarly save lr
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* and avoid it being modified by the branch and link
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* calls. This function is used very early in the secondary
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* CPU boot, and no stack is available at this point.
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*/
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mov r0, lr
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mov r0, lr
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bl ll_get_coherency_base
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bl ll_get_cpuid
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mov lr, r0
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bl ll_get_coherency_cpumask
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
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1:
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ldrex r2, [r0]
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@ -82,13 +99,15 @@ ENDPROC(ll_add_cpu_to_smp_group)
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ENTRY(ll_enable_coherency)
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/*
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* r0 being untouched in ll_get_coherency_base and
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* ll_get_cpuid, we can use it to save lr modifing it with the
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* following bl
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* As r0 is not modified by ll_get_coherency_base() and
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* ll_get_coherency_cpumask(), we use it to temporarly save lr
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* and avoid it being modified by the branch and link
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* calls. This function is used very early in the secondary
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* CPU boot, and no stack is available at this point.
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*/
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mov r0, lr
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bl ll_get_coherency_base
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bl ll_get_cpuid
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bl ll_get_coherency_cpumask
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
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1:
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@ -104,14 +123,16 @@ ENDPROC(ll_enable_coherency)
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ENTRY(ll_disable_coherency)
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/*
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* r0 being untouched in ll_get_coherency_base and
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* ll_get_cpuid, we can use it to save lr modifing it with the
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* following bl
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* As r0 is not modified by ll_get_coherency_base() and
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* ll_get_coherency_cpumask(), we use it to temporarly save lr
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* and avoid it being modified by the branch and link
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* calls. This function is used very early in the secondary
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* CPU boot, and no stack is available at this point.
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*/
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mov r0, lr
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mov r0, lr
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bl ll_get_coherency_base
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bl ll_get_cpuid
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mov lr, r0
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bl ll_get_coherency_cpumask
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
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1:
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ldrex r2, [r0]
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