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ARM: EXYNOS: no more support non-DT for EXYNOS SoCs
As we discussed in mailing list, non-DT for EXYNOS SoCs will not be supported from v3.11. This patch removes regarding files for non-DT including board files and defconfig. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim
parent
317ddd256b
commit
383ffda2fa
@ -84,329 +84,11 @@ config SOC_EXYNOS5440
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help
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Enable EXYNOS5440 SoC support
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config EXYNOS_ATAGS
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bool "ATAGS based boot for EXYNOS (deprecated)"
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depends on !ARCH_MULTIPLATFORM
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depends on ATAGS
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default y
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help
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The EXYNOS platform is moving towards being completely probed
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through device tree. This enables support for board files using
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the traditional ATAGS boot format.
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Note that this option is not available for multiplatform builds.
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if EXYNOS_ATAGS
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config EXYNOS_DEV_DMA
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bool
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help
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Compile in amba device definitions for DMA controller
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config EXYNOS4_DEV_AHCI
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bool
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help
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Compile in platform device definitions for AHCI
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config EXYNOS4_SETUP_FIMD0
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bool
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help
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Common setup code for FIMD0.
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config EXYNOS4_DEV_USB_OHCI
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bool
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help
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Compile in platform device definition for USB OHCI
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config EXYNOS4_SETUP_I2C1
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bool
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help
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Common setup code for i2c bus 1.
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config EXYNOS4_SETUP_I2C2
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bool
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help
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Common setup code for i2c bus 2.
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config EXYNOS4_SETUP_I2C3
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bool
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help
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Common setup code for i2c bus 3.
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config EXYNOS4_SETUP_I2C4
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bool
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help
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Common setup code for i2c bus 4.
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config EXYNOS4_SETUP_I2C5
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bool
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help
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Common setup code for i2c bus 5.
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config EXYNOS4_SETUP_I2C6
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bool
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help
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Common setup code for i2c bus 6.
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config EXYNOS4_SETUP_I2C7
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bool
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help
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Common setup code for i2c bus 7.
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config EXYNOS4_SETUP_KEYPAD
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bool
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help
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Common setup code for keypad.
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config EXYNOS4_SETUP_SDHCI
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bool
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select EXYNOS4_SETUP_SDHCI_GPIO
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help
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Internal helper functions for EXYNOS4 based SDHCI systems.
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config EXYNOS4_SETUP_SDHCI_GPIO
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bool
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help
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Common setup code for SDHCI gpio.
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config EXYNOS4_SETUP_FIMC
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bool
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help
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Common setup code for the camera interfaces.
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config EXYNOS4_SETUP_USB_PHY
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bool
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help
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Common setup code for USB PHY controller
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config EXYNOS_SETUP_SPI
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bool
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help
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Common setup code for SPI GPIO configurations.
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# machine support
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if ARCH_EXYNOS4
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comment "EXYNOS4210 Boards"
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config MACH_SMDKC210
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bool "SMDKC210"
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select MACH_SMDKV310
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help
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Machine support for Samsung SMDKC210
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config MACH_SMDKV310
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bool "SMDKV310"
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select CPU_EXYNOS4210
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select EXYNOS4_DEV_AHCI
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select EXYNOS4_DEV_USB_OHCI
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_KEYPAD
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_SYSMMU
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select S3C24XX_PWM
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC1
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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select S3C_DEV_I2C1
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select S3C_DEV_RTC
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select S3C_DEV_USB_HSOTG
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select S3C_DEV_WDT
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select S5P_DEV_FIMC0
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select S5P_DEV_FIMC1
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select S5P_DEV_FIMC2
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select S5P_DEV_FIMC3
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select S5P_DEV_FIMD0
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select S5P_DEV_G2D
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select S5P_DEV_I2C_HDMIPHY
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select S5P_DEV_JPEG
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select S5P_DEV_MFC
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select S5P_DEV_TV
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select S5P_DEV_USB_EHCI
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_KEYPAD
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select SAMSUNG_DEV_PWM
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help
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Machine support for Samsung SMDKV310
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config MACH_ARMLEX4210
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bool "ARMLEX4210"
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select CPU_EXYNOS4210
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select EXYNOS4_DEV_AHCI
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS_DEV_DMA
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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select S3C_DEV_RTC
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select S3C_DEV_WDT
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help
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Machine support for Samsung ARMLEX4210 based on EXYNOS4210
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config MACH_UNIVERSAL_C210
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bool "Mobile UNIVERSAL_C210 Board"
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select CLKSRC_MMIO
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select CLKSRC_SAMSUNG_PWM
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select CPU_EXYNOS4210
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select EXYNOS4_SETUP_FIMC
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_I2C3
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select EXYNOS4_SETUP_I2C5
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_SYSMMU
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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select S3C_DEV_I2C1
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select S3C_DEV_I2C3
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select S3C_DEV_I2C5
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select S3C_DEV_USB_HSOTG
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select S5P_DEV_CSIS0
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select S5P_DEV_FIMC0
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select S5P_DEV_FIMC1
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select S5P_DEV_FIMC2
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select S5P_DEV_FIMC3
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select S5P_DEV_FIMD0
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select S5P_DEV_G2D
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select S5P_DEV_I2C_HDMIPHY
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select S5P_DEV_JPEG
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select S5P_DEV_MFC
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select S5P_DEV_ONENAND
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select S5P_DEV_TV
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select S5P_GPIO_INT
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select S5P_SETUP_MIPIPHY
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help
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Machine support for Samsung Mobile Universal S5PC210 Reference
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Board.
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config MACH_NURI
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bool "Mobile NURI Board"
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select CPU_EXYNOS4210
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select EXYNOS4_SETUP_FIMC
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_I2C3
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select EXYNOS4_SETUP_I2C5
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select EXYNOS4_SETUP_I2C6
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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select S3C_DEV_I2C1
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select S3C_DEV_I2C3
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select S3C_DEV_I2C5
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select S3C_DEV_I2C6
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select S3C_DEV_RTC
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select S3C_DEV_USB_HSOTG
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select S3C_DEV_WDT
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select S5P_DEV_CSIS0
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select S5P_DEV_FIMC0
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select S5P_DEV_FIMC1
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select S5P_DEV_FIMC2
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select S5P_DEV_FIMC3
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select S5P_DEV_FIMD0
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select S5P_DEV_G2D
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select S5P_DEV_JPEG
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select S5P_DEV_MFC
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select S5P_DEV_USB_EHCI
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select S5P_GPIO_INT
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select S5P_SETUP_MIPIPHY
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select SAMSUNG_DEV_ADC
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select SAMSUNG_DEV_PWM
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help
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Machine support for Samsung Mobile NURI Board.
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config MACH_ORIGEN
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bool "ORIGEN"
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select CPU_EXYNOS4210
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select EXYNOS4_DEV_USB_OHCI
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_SYSMMU
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select S3C24XX_PWM
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC2
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select S3C_DEV_RTC
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select S3C_DEV_USB_HSOTG
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select S3C_DEV_WDT
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select S5P_DEV_FIMC0
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select S5P_DEV_FIMC1
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select S5P_DEV_FIMC2
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select S5P_DEV_FIMC3
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select S5P_DEV_FIMD0
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select S5P_DEV_G2D
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select S5P_DEV_I2C_HDMIPHY
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select S5P_DEV_JPEG
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select S5P_DEV_MFC
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select S5P_DEV_TV
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select S5P_DEV_USB_EHCI
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_PWM
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help
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Machine support for ORIGEN based on Samsung EXYNOS4210
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comment "EXYNOS4212 Boards"
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config MACH_SMDK4212
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bool "SMDK4212"
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_I2C3
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select EXYNOS4_SETUP_I2C7
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select EXYNOS4_SETUP_KEYPAD
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_SYSMMU
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select S3C24XX_PWM
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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select S3C_DEV_I2C1
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select S3C_DEV_I2C3
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select S3C_DEV_I2C7
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select S3C_DEV_RTC
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select S3C_DEV_USB_HSOTG
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select S3C_DEV_WDT
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select S5P_DEV_FIMC0
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select S5P_DEV_FIMC1
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select S5P_DEV_FIMC2
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select S5P_DEV_FIMC3
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select S5P_DEV_FIMD0
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select S5P_DEV_MFC
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_KEYPAD
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select SAMSUNG_DEV_PWM
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select SOC_EXYNOS4212
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help
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Machine support for Samsung SMDK4212
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comment "EXYNOS4412 Boards"
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config MACH_SMDK4412
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bool "SMDK4412"
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select MACH_SMDK4212
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select SOC_EXYNOS4412
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help
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Machine support for Samsung SMDK4412
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endif
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endif
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comment "Flattened Device Tree based board for EXYNOS SoCs"
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config MACH_EXYNOS4_DT
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bool "Samsung Exynos4 Machine using device tree"
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default y
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depends on ARCH_EXYNOS4
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select ARM_AMBA
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select CLKSRC_OF
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@ -32,16 +32,6 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
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# machine support
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obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o
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obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
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obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
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obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
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obj-$(CONFIG_MACH_NURI) += mach-nuri.o
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obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
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obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
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obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
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obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
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obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
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@ -49,21 +39,5 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
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obj-y += dev-uart.o
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obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
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obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
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obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
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obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
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obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
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obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
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obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
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obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
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obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
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obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
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obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
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obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
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obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
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obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
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obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
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obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
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obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
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@ -353,7 +353,6 @@ void __init exynos_init_late(void)
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exynos_pm_late_initcall();
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}
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#ifdef CONFIG_OF
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int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
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int depth, void *data)
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{
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@ -376,7 +375,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
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iotable_init(&iodesc, 1);
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return 1;
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}
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#endif
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/*
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* exynos_map_io
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@ -388,11 +386,9 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
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{
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debug_ll_io_init();
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#ifdef CONFIG_OF
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if (initial_boot_params)
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of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
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else
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#endif
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iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
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if (mach_desc)
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@ -475,10 +471,8 @@ void __init exynos_init_time(void)
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};
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if (of_have_populated_dt()) {
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#ifdef CONFIG_OF
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of_clk_init(NULL);
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clocksource_of_init();
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#endif
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} else {
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/* todo: remove after migrating legacy E4 platforms to dt */
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#ifdef CONFIG_ARCH_EXYNOS4
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@ -517,10 +511,8 @@ void __init exynos4_init_irq(void)
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if (!of_have_populated_dt())
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gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
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#ifdef CONFIG_OF
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else
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irqchip_init();
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#endif
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if (!of_have_populated_dt())
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combiner_init(S5P_VA_COMBINER_BASE, NULL,
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@ -531,9 +523,7 @@ void __init exynos4_init_irq(void)
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void __init exynos5_init_irq(void)
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{
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#ifdef CONFIG_OF
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irqchip_init();
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#endif
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gic_arch_extn.irq_set_wake = s3c_irq_wake;
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}
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@ -1,255 +0,0 @@
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/* linux/arch/arm/mach-exynos4/dev-ahci.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - AHCI support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/ahci_platform.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
/* PHY Control Register */
|
||||
#define SATA_CTRL0 0x0
|
||||
/* PHY Link Control Register */
|
||||
#define SATA_CTRL1 0x4
|
||||
/* PHY Status Register */
|
||||
#define SATA_PHY_STATUS 0x8
|
||||
|
||||
#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
|
||||
#define SATA_CTRL0_SPEED_MODE (1 << 26)
|
||||
#define SATA_CTRL0_M_PHY_CAL (1 << 19)
|
||||
#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
|
||||
#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
|
||||
#define SATA_CTRL0_PHY_POR_N (1 << 8)
|
||||
|
||||
#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
|
||||
#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
|
||||
#define SATA_CTRL1_RST_RX_N (1 << 6)
|
||||
#define SATA_CTRL1_RST_TX_N (1 << 5)
|
||||
|
||||
#define SATA_PHY_STATUS_CMU_OK (1 << 18)
|
||||
#define SATA_PHY_STATUS_LANE_OK (1 << 16)
|
||||
|
||||
#define LANE0 0x200
|
||||
#define COM_LANE 0xA00
|
||||
|
||||
#define HOST_PORTS_IMPL 0xC
|
||||
#define SCLK_SATA_FREQ (67 * MHZ)
|
||||
|
||||
static void __iomem *phy_base, *phy_ctrl;
|
||||
|
||||
struct phy_reg {
|
||||
u8 reg;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
/* SATA PHY setup */
|
||||
static const struct phy_reg exynos4_sataphy_cmu[] = {
|
||||
{ 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
|
||||
{ 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
|
||||
{ 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
|
||||
{ 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
|
||||
{ 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
|
||||
{ 0x6b, 0xc8 }, { 0x6c, 0x06 },
|
||||
};
|
||||
|
||||
static const struct phy_reg exynos4_sataphy_lane[] = {
|
||||
{ 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
|
||||
{ 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
|
||||
{ 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
|
||||
{ 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
|
||||
{ 0x51, 0x0f },
|
||||
};
|
||||
|
||||
static const struct phy_reg exynos4_sataphy_comlane[] = {
|
||||
{ 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
|
||||
{ 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
|
||||
{ 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
|
||||
{ 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
|
||||
{ 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
|
||||
{ 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
|
||||
{ 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
|
||||
{ 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
|
||||
{ 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
|
||||
{ 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
|
||||
{ 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
|
||||
{ 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
|
||||
{ 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
|
||||
{ 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
|
||||
};
|
||||
|
||||
static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/* wait for maximum of 3 sec */
|
||||
timeout = jiffies + msecs_to_jiffies(3000);
|
||||
while (!(__raw_readl(reg) & bit)) {
|
||||
if (time_after(jiffies, timeout))
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ahci_phy_init(void __iomem *mmio)
|
||||
{
|
||||
int i, ctrl0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
|
||||
__raw_writeb(exynos4_sataphy_cmu[i].val,
|
||||
phy_base + (exynos4_sataphy_cmu[i].reg * 4));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
|
||||
__raw_writeb(exynos4_sataphy_lane[i].val,
|
||||
phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
|
||||
__raw_writeb(exynos4_sataphy_comlane[i].val,
|
||||
phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
|
||||
|
||||
__raw_writeb(0x07, phy_base);
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
|
||||
SATA_PHY_STATUS_CMU_OK) < 0) {
|
||||
printk(KERN_ERR "PHY CMU not ready\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
__raw_writeb(0x03, phy_base + (COM_LANE * 4));
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
|
||||
SATA_PHY_STATUS_LANE_OK) < 0) {
|
||||
printk(KERN_ERR "PHY LANE not ready\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_M_PHY_CAL;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
|
||||
{
|
||||
struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
|
||||
int val, ret;
|
||||
|
||||
phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
|
||||
if (!phy_base) {
|
||||
dev_err(dev, "failed to allocate memory for SATA PHY\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
|
||||
if (!phy_ctrl) {
|
||||
dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
|
||||
ret = -ENOMEM;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
clk_sata = clk_get(dev, "sata");
|
||||
if (IS_ERR(clk_sata)) {
|
||||
dev_err(dev, "failed to get sata clock\n");
|
||||
ret = PTR_ERR(clk_sata);
|
||||
clk_sata = NULL;
|
||||
goto err2;
|
||||
|
||||
}
|
||||
clk_enable(clk_sata);
|
||||
|
||||
clk_sataphy = clk_get(dev, "sataphy");
|
||||
if (IS_ERR(clk_sataphy)) {
|
||||
dev_err(dev, "failed to get sataphy clock\n");
|
||||
ret = PTR_ERR(clk_sataphy);
|
||||
clk_sataphy = NULL;
|
||||
goto err3;
|
||||
}
|
||||
clk_enable(clk_sataphy);
|
||||
|
||||
clk_sclk_sata = clk_get(dev, "sclk_sata");
|
||||
if (IS_ERR(clk_sclk_sata)) {
|
||||
dev_err(dev, "failed to get sclk_sata\n");
|
||||
ret = PTR_ERR(clk_sclk_sata);
|
||||
clk_sclk_sata = NULL;
|
||||
goto err4;
|
||||
}
|
||||
clk_enable(clk_sclk_sata);
|
||||
clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
|
||||
|
||||
__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
|
||||
|
||||
/* Enable PHY link control */
|
||||
val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
|
||||
SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
|
||||
__raw_writel(val, phy_ctrl + SATA_CTRL1);
|
||||
|
||||
/* Set communication speed as 3Gbps and enable PHY power */
|
||||
val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
|
||||
SATA_CTRL0_PHY_POR_N;
|
||||
__raw_writel(val, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
/* Port0 is available */
|
||||
__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
|
||||
|
||||
return ahci_phy_init(mmio);
|
||||
|
||||
err4:
|
||||
clk_disable(clk_sataphy);
|
||||
clk_put(clk_sataphy);
|
||||
err3:
|
||||
clk_disable(clk_sata);
|
||||
clk_put(clk_sata);
|
||||
err2:
|
||||
iounmap(phy_ctrl);
|
||||
err1:
|
||||
iounmap(phy_base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct ahci_platform_data exynos4_ahci_pdata = {
|
||||
.init = exynos4_ahci_init,
|
||||
};
|
||||
|
||||
static struct resource exynos4_ahci_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
|
||||
};
|
||||
|
||||
static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device exynos4_device_ahci = {
|
||||
.name = "ahci",
|
||||
.id = -1,
|
||||
.resource = exynos4_ahci_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_ahci_resource),
|
||||
.dev = {
|
||||
.platform_data = &exynos4_ahci_pdata,
|
||||
.dma_mask = &exynos4_ahci_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
@ -1,52 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos/dev-ohci.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS - OHCI support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/platform_data/usb-ohci-exynos.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
#include <plat/usb-phy.h>
|
||||
|
||||
static struct resource exynos4_ohci_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
|
||||
};
|
||||
|
||||
static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device exynos4_device_ohci = {
|
||||
.name = "exynos-ohci",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(exynos4_ohci_resource),
|
||||
.resource = exynos4_ohci_resource,
|
||||
.dev = {
|
||||
.dma_mask = &exynos4_ohci_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
}
|
||||
};
|
||||
|
||||
void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
|
||||
{
|
||||
struct exynos4_ohci_platdata *npd;
|
||||
|
||||
npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
|
||||
&exynos4_device_ohci);
|
||||
|
||||
if (!npd->phy_init)
|
||||
npd->phy_init = s5p_usb_phy_init;
|
||||
if (!npd->phy_exit)
|
||||
npd->phy_exit = s5p_usb_phy_exit;
|
||||
}
|
||||
@ -1,322 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos4/dma.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
|
||||
* Jaswinder Singh <jassi.brar@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/pl330.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
static u8 exynos4210_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_MSM_REQ0,
|
||||
DMACH_MSM_REQ2,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
};
|
||||
|
||||
static u8 exynos4212_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI5,
|
||||
};
|
||||
|
||||
static u8 exynos5250_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI6,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos_pdma0_pdata;
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
|
||||
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
|
||||
|
||||
static u8 exynos4210_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_MSM_REQ1,
|
||||
DMACH_MSM_REQ3,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
};
|
||||
|
||||
static u8 exynos4212_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_SLIMBUS0AUX_RX,
|
||||
DMACH_SLIMBUS0AUX_TX,
|
||||
DMACH_SPDIF,
|
||||
DMACH_MIPI_HSI6,
|
||||
DMACH_MIPI_HSI7,
|
||||
};
|
||||
|
||||
static u8 exynos5250_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_PWM,
|
||||
DMACH_SPDIF,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_SLIMBUS0AUX_RX,
|
||||
DMACH_SLIMBUS0AUX_TX,
|
||||
DMACH_DISP1,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_MIPI_HSI5,
|
||||
DMACH_MIPI_HSI7,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos_pdma1_pdata;
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
|
||||
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
|
||||
|
||||
static u8 mdma_peri[] = {
|
||||
DMACH_MTOM_0,
|
||||
DMACH_MTOM_1,
|
||||
DMACH_MTOM_2,
|
||||
DMACH_MTOM_3,
|
||||
DMACH_MTOM_4,
|
||||
DMACH_MTOM_5,
|
||||
DMACH_MTOM_6,
|
||||
DMACH_MTOM_7,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos_mdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(mdma_peri),
|
||||
.peri_id = mdma_peri,
|
||||
};
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
|
||||
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
|
||||
|
||||
static int __init exynos_dma_init(void)
|
||||
{
|
||||
if (of_have_populated_dt())
|
||||
return 0;
|
||||
|
||||
if (soc_is_exynos4210()) {
|
||||
exynos_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma0_peri);
|
||||
exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
|
||||
exynos_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma1_peri);
|
||||
exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
|
||||
|
||||
if (samsung_rev() == EXYNOS4210_REV_0)
|
||||
exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
|
||||
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||
exynos_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma0_peri);
|
||||
exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
|
||||
exynos_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma1_peri);
|
||||
exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
|
||||
} else if (soc_is_exynos5250()) {
|
||||
exynos_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos5250_pdma0_peri);
|
||||
exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
|
||||
exynos_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos5250_pdma1_peri);
|
||||
exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
|
||||
|
||||
exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
|
||||
exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
|
||||
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
|
||||
exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
|
||||
exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
|
||||
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
|
||||
exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
|
||||
exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
|
||||
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
|
||||
}
|
||||
|
||||
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
|
||||
amba_device_register(&exynos_pdma0_device, &iomem_resource);
|
||||
|
||||
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos_pdma1_device, &iomem_resource);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos_mdma1_device, &iomem_resource);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos_dma_init);
|
||||
@ -84,7 +84,6 @@ static struct exynos_pm_domain PD = { \
|
||||
}, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
|
||||
struct device *dev)
|
||||
{
|
||||
@ -193,12 +192,6 @@ static __init int exynos_pm_dt_parse_domains(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static __init int exynos_pm_dt_parse_domains(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
|
||||
struct exynos_pm_domain *pd)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user