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ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init

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We don't need to re-pass the base address for the CPU interfaces to the
GIC for secondary CPUs, as it will never be different from the boot CPU
- and even if it was, we'd overwrite the boot CPU's base address.

Get rid of this argument, and rename to gic_secondary_init().

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2010-12-04 16:01:03 +00:00
parent b580b899dd
commit 384895330e
8 changed files with 13 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/common/gic.c
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@ -284,7 +284,7 @@ static void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
writel(1, base + GIC_DIST_CTRL);
}
void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
static void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
{
void __iomem *dist_base;
int i;
@ -321,6 +321,11 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
gic_cpu_init(gic_nr, cpu_base);
}
void __cpuinit gic_secondary_init(unsigned int gic_nr)
{
gic_cpu_init(gic_nr, gic_data[gic_nr].cpu_base);
}
#ifdef CONFIG_SMP
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{

2
arch/arm/include/asm/hardware/gic.h
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@ -33,8 +33,8 @@
#define GIC_DIST_SOFTINT 0xf00
#ifndef __ASSEMBLY__
void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
#endif

2
arch/arm/mach-omap2/omap-smp.c
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@ -50,7 +50,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, gic_cpu_base_addr);
gic_secondary_init(0);
/*
* Synchronise with the boot thread.

2
arch/arm/mach-realview/platsmp.c
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@ -69,7 +69,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, gic_cpu_base_addr);
gic_secondary_init(0);
/*
* let the primary processor know we're out of the

2
arch/arm/mach-s5pv310/platsmp.c
View File

@ -54,7 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, gic_cpu_base_addr);
gic_secondary_init(0);
/*
* let the primary processor know we're out of the

2
arch/arm/mach-tegra/platsmp.c
View File

@ -48,7 +48,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
gic_secondary_init(0);
/*
* Synchronise with the boot thread.

2
arch/arm/mach-ux500/platsmp.c
View File

@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
gic_secondary_init(0);
/*
* let the primary processor know we're out of the

2
arch/arm/mach-vexpress/platsmp.c
View File

@ -51,7 +51,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, gic_cpu_base_addr);
gic_secondary_init(0);
/*
* let the primary processor know we're out of the