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ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init
We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -284,7 +284,7 @@ static void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
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writel(1, base + GIC_DIST_CTRL);
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}
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void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
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static void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
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{
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void __iomem *dist_base;
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int i;
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@ -321,6 +321,11 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
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gic_cpu_init(gic_nr, cpu_base);
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}
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void __cpuinit gic_secondary_init(unsigned int gic_nr)
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{
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gic_cpu_init(gic_nr, gic_data[gic_nr].cpu_base);
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}
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#ifdef CONFIG_SMP
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void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
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{
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@ -33,8 +33,8 @@
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#define GIC_DIST_SOFTINT 0xf00
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#ifndef __ASSEMBLY__
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void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
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void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
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void gic_secondary_init(unsigned int);
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void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
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void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
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#endif
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@ -50,7 +50,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, gic_cpu_base_addr);
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gic_secondary_init(0);
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/*
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* Synchronise with the boot thread.
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@ -69,7 +69,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, gic_cpu_base_addr);
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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@ -54,7 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, gic_cpu_base_addr);
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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@ -48,7 +48,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
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gic_secondary_init(0);
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/*
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* Synchronise with the boot thread.
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@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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@ -51,7 +51,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, gic_cpu_base_addr);
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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