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ASoC: Add WM9090 amplifier driver

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The WM9090 is a high performance low power audio subsystem, including
headphone and class D speaker drivers.

Note that this driver is a standalone CODEC driver and so is only
immediately suitable for use with the WM9090 as a standalone sound card
taking line inputs, or with a DAC with no software control.  The pending
ASoC multi-CODEC support will expand the range of systems that can use
the driver, or system-specific adaptations can be made.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Mark Brown 2010-04-28 18:36:10 +01:00
parent dde3a7e9cb
commit 39b8eab7e7
5 changed files with 1522 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
include/sound/wm9090.h Normal file
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@ -0,0 +1,28 @@
/*
* linux/sound/wm9090.h -- Platform data for WM9090
*
* Copyright 2009, 2010 Wolfson Microelectronics. PLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_WM9090_H
#define __LINUX_SND_WM9090_H
struct wm9090_platform_data {
/* Line inputs 1 & 2 can optionally be differential */
unsigned int lin1_diff:1;
unsigned int lin2_diff:1;
/* AGC configuration. This is intended to protect the speaker
* against overdriving and will therefore depend on the
* hardware setup with incorrect runtime configuration
* potentially causing hardware damage.
*/
unsigned int agc_ena:1;
u16 agc[3];
};
#endif

4
sound/soc/codecs/Kconfig
View File

@ -66,6 +66,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_WM8993 if I2C
select SND_SOC_WM8994 if MFD_WM8994
select SND_SOC_WM9081 if I2C
select SND_SOC_WM9090 if I2C
select SND_SOC_WM9705 if SND_SOC_AC97_BUS
select SND_SOC_WM9712 if SND_SOC_AC97_BUS
select SND_SOC_WM9713 if SND_SOC_AC97_BUS
@ -277,3 +278,6 @@ config SND_SOC_TPA6130A2
config SND_SOC_WM2000
tristate
config SND_SOC_WM9090
tristate

2
sound/soc/codecs/Makefile
View File

@ -61,6 +61,7 @@ snd-soc-wm-hubs-objs := wm_hubs.o
snd-soc-max9877-objs := max9877.o
snd-soc-tpa6130a2-objs := tpa6130a2.o
snd-soc-wm2000-objs := wm2000.o
snd-soc-wm9090-objs := wm9090.o
obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o
obj-$(CONFIG_SND_SOC_AD1836) += snd-soc-ad1836.o
@ -125,3 +126,4 @@ obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o
obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o
obj-$(CONFIG_SND_SOC_WM9090) += snd-soc-wm9090.o

773
sound/soc/codecs/wm9090.c Normal file
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@ -0,0 +1,773 @@
/*
* ALSA SoC WM9090 driver
*
* Copyright 2009, 2010 Wolfson Microelectronics
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/wm9090.h>
#include "wm9090.h"
static struct snd_soc_codec *wm9090_codec;
static const u16 wm9090_reg_defaults[] = {
0x9093, /* R0 - Software Reset */
0x0006, /* R1 - Power Management (1) */
0x6000, /* R2 - Power Management (2) */
0x0000, /* R3 - Power Management (3) */
0x0000, /* R4 */
0x0000, /* R5 */
0x01C0, /* R6 - Clocking 1 */
0x0000, /* R7 */
0x0000, /* R8 */
0x0000, /* R9 */
0x0000, /* R10 */
0x0000, /* R11 */
0x0000, /* R12 */
0x0000, /* R13 */
0x0000, /* R14 */
0x0000, /* R15 */
0x0000, /* R16 */
0x0000, /* R17 */
0x0000, /* R18 */
0x0000, /* R19 */
0x0000, /* R20 */
0x0000, /* R21 */
0x0003, /* R22 - IN1 Line Control */
0x0003, /* R23 - IN2 Line Control */
0x0083, /* R24 - IN1 Line Input A Volume */
0x0083, /* R25 - IN1 Line Input B Volume */
0x0083, /* R26 - IN2 Line Input A Volume */
0x0083, /* R27 - IN2 Line Input B Volume */
0x002D, /* R28 - Left Output Volume */
0x002D, /* R29 - Right Output Volume */
0x0000, /* R30 */
0x0000, /* R31 */
0x0000, /* R32 */
0x0000, /* R33 */
0x0100, /* R34 - SPKMIXL Attenuation */
0x0000, /* R35 */
0x0010, /* R36 - SPKOUT Mixers */
0x0140, /* R37 - ClassD3 */
0x0039, /* R38 - Speaker Volume Left */
0x0000, /* R39 */
0x0000, /* R40 */
0x0000, /* R41 */
0x0000, /* R42 */
0x0000, /* R43 */
0x0000, /* R44 */
0x0000, /* R45 - Output Mixer1 */
0x0000, /* R46 - Output Mixer2 */
0x0100, /* R47 - Output Mixer3 */
0x0100, /* R48 - Output Mixer4 */
0x0000, /* R49 */
0x0000, /* R50 */
0x0000, /* R51 */
0x0000, /* R52 */
0x0000, /* R53 */
0x0000, /* R54 - Speaker Mixer */
0x0000, /* R55 */
0x0000, /* R56 */
0x000D, /* R57 - AntiPOP2 */
0x0000, /* R58 */
0x0000, /* R59 */
0x0000, /* R60 */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x0000, /* R64 */
0x0000, /* R65 */
0x0000, /* R66 */
0x0000, /* R67 */
0x0000, /* R68 */
0x0000, /* R69 */
0x0000, /* R70 - Write Sequencer 0 */
0x0000, /* R71 - Write Sequencer 1 */
0x0000, /* R72 - Write Sequencer 2 */
0x0000, /* R73 - Write Sequencer 3 */
0x0000, /* R74 - Write Sequencer 4 */
0x0000, /* R75 - Write Sequencer 5 */
0x1F25, /* R76 - Charge Pump 1 */
0x0000, /* R77 */
0x0000, /* R78 */
0x0000, /* R79 */
0x0000, /* R80 */
0x0000, /* R81 */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 - DC Servo 0 */
0x054A, /* R85 - DC Servo 1 */
0x0000, /* R86 */
0x0000, /* R87 - DC Servo 3 */
0x0000, /* R88 - DC Servo Readback 0 */
0x0000, /* R89 - DC Servo Readback 1 */
0x0000, /* R90 - DC Servo Readback 2 */
0x0000, /* R91 */
0x0000, /* R92 */
0x0000, /* R93 */
0x0000, /* R94 */
0x0000, /* R95 */
0x0100, /* R96 - Analogue HP 0 */
0x0000, /* R97 */
0x8640, /* R98 - AGC Control 0 */
0xC000, /* R99 - AGC Control 1 */
0x0200, /* R100 - AGC Control 2 */
};
/* This struct is used to save the context */
struct wm9090_priv {
/* We're not really registering as a CODEC since ASoC core
* does not yet support multiple CODECs but having the CODEC
* structure means we can reuse some of the ASoC core
* features.
*/
struct snd_soc_codec codec;
struct mutex mutex;
u16 reg_cache[WM9090_MAX_REGISTER + 1];
struct wm9090_platform_data pdata;
};
static int wm9090_volatile(unsigned int reg)
{
switch (reg) {
case WM9090_SOFTWARE_RESET:
case WM9090_DC_SERVO_0:
case WM9090_DC_SERVO_READBACK_0:
case WM9090_DC_SERVO_READBACK_1:
case WM9090_DC_SERVO_READBACK_2:
return 1;
default:
return 0;
}
}
static void wait_for_dc_servo(struct snd_soc_codec *codec)
{
unsigned int reg;
int count = 0;
dev_dbg(codec->dev, "Waiting for DC servo...\n");
do {
count++;
msleep(1);
reg = snd_soc_read(codec, WM9090_DC_SERVO_READBACK_0);
dev_dbg(codec->dev, "DC servo status: %x\n", reg);
} while ((reg & WM9090_DCS_CAL_COMPLETE_MASK)
!= WM9090_DCS_CAL_COMPLETE_MASK && count < 1000);
if ((reg & WM9090_DCS_CAL_COMPLETE_MASK)
!= WM9090_DCS_CAL_COMPLETE_MASK)
dev_err(codec->dev, "Timed out waiting for DC Servo\n");
}
static const unsigned int in_tlv[] = {
TLV_DB_RANGE_HEAD(6),
0, 0, TLV_DB_SCALE_ITEM(-600, 0, 0),
1, 3, TLV_DB_SCALE_ITEM(-350, 350, 0),
4, 6, TLV_DB_SCALE_ITEM(600, 600, 0),
};
static const unsigned int mix_tlv[] = {
TLV_DB_RANGE_HEAD(4),
0, 2, TLV_DB_SCALE_ITEM(-1200, 300, 0),
3, 3, TLV_DB_SCALE_ITEM(0, 0, 0),
};
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const unsigned int spkboost_tlv[] = {
TLV_DB_RANGE_HEAD(7),
0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
};
static const struct snd_kcontrol_new wm9090_controls[] = {
SOC_SINGLE_TLV("IN1A Volume", WM9090_IN1_LINE_INPUT_A_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN1A Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1A ZC Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("IN2A Volume", WM9090_IN2_LINE_INPUT_A_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN2A Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2A ZC Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 6, 1, 0),
SOC_SINGLE("MIXOUTL Switch", WM9090_OUTPUT_MIXER3, 8, 1, 1),
SOC_SINGLE_TLV("MIXOUTL IN1A Volume", WM9090_OUTPUT_MIXER3, 6, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTL IN2A Volume", WM9090_OUTPUT_MIXER3, 2, 3, 1,
mix_tlv),
SOC_SINGLE("MIXOUTR Switch", WM9090_OUTPUT_MIXER4, 8, 1, 1),
SOC_SINGLE_TLV("MIXOUTR IN1A Volume", WM9090_OUTPUT_MIXER4, 6, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTR IN2A Volume", WM9090_OUTPUT_MIXER4, 2, 3, 1,
mix_tlv),
SOC_SINGLE("SPKMIX Switch", WM9090_SPKMIXL_ATTENUATION, 8, 1, 1),
SOC_SINGLE_TLV("SPKMIX IN1A Volume", WM9090_SPKMIXL_ATTENUATION, 6, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("SPKMIX IN2A Volume", WM9090_SPKMIXL_ATTENUATION, 2, 3, 1,
mix_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", WM9090_LEFT_OUTPUT_VOLUME,
WM9090_RIGHT_OUTPUT_VOLUME, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Headphone Switch", WM9090_LEFT_OUTPUT_VOLUME,
WM9090_RIGHT_OUTPUT_VOLUME, 6, 1, 1),
SOC_DOUBLE_R("Headphone ZC Switch", WM9090_LEFT_OUTPUT_VOLUME,
WM9090_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
SOC_SINGLE_TLV("Speaker Volume", WM9090_SPEAKER_VOLUME_LEFT, 0, 63, 0,
out_tlv),
SOC_SINGLE("Speaker Switch", WM9090_SPEAKER_VOLUME_LEFT, 6, 1, 1),
SOC_SINGLE("Speaker ZC Switch", WM9090_SPEAKER_VOLUME_LEFT, 7, 1, 0),
SOC_SINGLE_TLV("Speaker Boost Volume", WM9090_CLASSD3, 3, 7, 0, spkboost_tlv),
};
static const struct snd_kcontrol_new wm9090_in1_se_controls[] = {
SOC_SINGLE_TLV("IN1B Volume", WM9090_IN1_LINE_INPUT_B_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN1B Switch", WM9090_IN1_LINE_INPUT_B_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1B ZC Switch", WM9090_IN1_LINE_INPUT_B_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("SPKMIX IN1B Volume", WM9090_SPKMIXL_ATTENUATION, 4, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTL IN1B Volume", WM9090_OUTPUT_MIXER3, 4, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTR IN1B Volume", WM9090_OUTPUT_MIXER4, 4, 3, 1,
mix_tlv),
};
static const struct snd_kcontrol_new wm9090_in2_se_controls[] = {
SOC_SINGLE_TLV("IN2B Volume", WM9090_IN2_LINE_INPUT_B_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN2B Switch", WM9090_IN2_LINE_INPUT_B_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2B ZC Switch", WM9090_IN2_LINE_INPUT_B_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("SPKMIX IN2B Volume", WM9090_SPKMIXL_ATTENUATION, 0, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTL IN2B Volume", WM9090_OUTPUT_MIXER3, 0, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTR IN2B Volume", WM9090_OUTPUT_MIXER4, 0, 3, 1,
mix_tlv),
};
static int hp_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
unsigned int reg = snd_soc_read(codec, WM9090_ANALOGUE_HP_0);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, WM9090_CHARGE_PUMP_1,
WM9090_CP_ENA, WM9090_CP_ENA);
msleep(5);
snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_1,
WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA,
WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA);
reg |= WM9090_HPOUT1L_DLY | WM9090_HPOUT1R_DLY;
snd_soc_write(codec, WM9090_ANALOGUE_HP_0, reg);
/* Start the DC servo. We don't currently use the
* ability to save the state since we don't have full
* control of the analogue paths and they can change
* DC offsets; see the WM8904 driver for an example of
* doing so.
*/
snd_soc_write(codec, WM9090_DC_SERVO_0,
WM9090_DCS_ENA_CHAN_0 |
WM9090_DCS_ENA_CHAN_1 |
WM9090_DCS_TRIG_STARTUP_1 |
WM9090_DCS_TRIG_STARTUP_0);
wait_for_dc_servo(codec);
reg |= WM9090_HPOUT1R_OUTP | WM9090_HPOUT1R_RMV_SHORT |
WM9090_HPOUT1L_OUTP | WM9090_HPOUT1L_RMV_SHORT;
snd_soc_write(codec, WM9090_ANALOGUE_HP_0, reg);
break;
case SND_SOC_DAPM_PRE_PMD:
reg &= ~(WM9090_HPOUT1L_RMV_SHORT |
WM9090_HPOUT1L_DLY |
WM9090_HPOUT1L_OUTP |
WM9090_HPOUT1R_RMV_SHORT |
WM9090_HPOUT1R_DLY |
WM9090_HPOUT1R_OUTP);
snd_soc_write(codec, WM9090_ANALOGUE_HP_0, reg);
snd_soc_write(codec, WM9090_DC_SERVO_0, 0);
snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_1,
WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA,
0);
snd_soc_update_bits(codec, WM9090_CHARGE_PUMP_1,
WM9090_CP_ENA, 0);
break;
}
return 0;
}
static const struct snd_kcontrol_new spkmix[] = {
SOC_DAPM_SINGLE("IN1A Switch", WM9090_SPEAKER_MIXER, 6, 1, 0),
SOC_DAPM_SINGLE("IN1B Switch", WM9090_SPEAKER_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("IN2A Switch", WM9090_SPEAKER_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("IN2B Switch", WM9090_SPEAKER_MIXER, 0, 1, 0),
};
static const struct snd_kcontrol_new spkout[] = {
SOC_DAPM_SINGLE("Mixer Switch", WM9090_SPKOUT_MIXERS, 4, 1, 0),
};
static const struct snd_kcontrol_new mixoutl[] = {
SOC_DAPM_SINGLE("IN1A Switch", WM9090_OUTPUT_MIXER1, 6, 1, 0),
SOC_DAPM_SINGLE("IN1B Switch", WM9090_OUTPUT_MIXER1, 4, 1, 0),
SOC_DAPM_SINGLE("IN2A Switch", WM9090_OUTPUT_MIXER1, 2, 1, 0),
SOC_DAPM_SINGLE("IN2B Switch", WM9090_OUTPUT_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new mixoutr[] = {
SOC_DAPM_SINGLE("IN1A Switch", WM9090_OUTPUT_MIXER2, 6, 1, 0),
SOC_DAPM_SINGLE("IN1B Switch", WM9090_OUTPUT_MIXER2, 4, 1, 0),
SOC_DAPM_SINGLE("IN2A Switch", WM9090_OUTPUT_MIXER2, 2, 1, 0),
SOC_DAPM_SINGLE("IN2B Switch", WM9090_OUTPUT_MIXER2, 0, 1, 0),
};
static const struct snd_soc_dapm_widget wm9090_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1+"),
SND_SOC_DAPM_INPUT("IN1-"),
SND_SOC_DAPM_INPUT("IN2+"),
SND_SOC_DAPM_INPUT("IN2-"),
SND_SOC_DAPM_SUPPLY("OSC", WM9090_POWER_MANAGEMENT_1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN1A PGA", WM9090_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN1B PGA", WM9090_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN2A PGA", WM9090_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN2B PGA", WM9090_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SPKMIX", WM9090_POWER_MANAGEMENT_3, 3, 0,
spkmix, ARRAY_SIZE(spkmix)),
SND_SOC_DAPM_MIXER("MIXOUTL", WM9090_POWER_MANAGEMENT_3, 5, 0,
mixoutl, ARRAY_SIZE(mixoutl)),
SND_SOC_DAPM_MIXER("MIXOUTR", WM9090_POWER_MANAGEMENT_3, 4, 0,
mixoutr, ARRAY_SIZE(mixoutr)),
SND_SOC_DAPM_PGA_E("HP PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
hp_ev, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("SPKPGA", WM9090_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SPKOUT", WM9090_POWER_MANAGEMENT_1, 12, 0,
spkout, ARRAY_SIZE(spkout)),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("Speaker"),
};
static const struct snd_soc_dapm_route audio_map[] = {
{ "IN1A PGA", NULL, "IN1+" },
{ "IN2A PGA", NULL, "IN2+" },
{ "SPKMIX", "IN1A Switch", "IN1A PGA" },
{ "SPKMIX", "IN2A Switch", "IN2A PGA" },
{ "MIXOUTL", "IN1A Switch", "IN1A PGA" },
{ "MIXOUTL", "IN2A Switch", "IN2A PGA" },
{ "MIXOUTR", "IN1A Switch", "IN1A PGA" },
{ "MIXOUTR", "IN2A Switch", "IN2A PGA" },
{ "HP PGA", NULL, "OSC" },
{ "HP PGA", NULL, "MIXOUTL" },
{ "HP PGA", NULL, "MIXOUTR" },
{ "HPL", NULL, "HP PGA" },
{ "HPR", NULL, "HP PGA" },
{ "SPKPGA", NULL, "OSC" },
{ "SPKPGA", NULL, "SPKMIX" },
{ "SPKOUT", "Mixer Switch", "SPKPGA" },
{ "Speaker", NULL, "SPKOUT" },
};
static const struct snd_soc_dapm_route audio_map_in1_se[] = {
{ "IN1B PGA", NULL, "IN1-" },
{ "SPKMIX", "IN1B Switch", "IN1B PGA" },
{ "MIXOUTL", "IN1B Switch", "IN1B PGA" },
{ "MIXOUTR", "IN1B Switch", "IN1B PGA" },
};
static const struct snd_soc_dapm_route audio_map_in1_diff[] = {
{ "IN1A PGA", NULL, "IN1-" },
};
static const struct snd_soc_dapm_route audio_map_in2_se[] = {
{ "IN2B PGA", NULL, "IN2-" },
{ "SPKMIX", "IN2B Switch", "IN2B PGA" },
{ "MIXOUTL", "IN2B Switch", "IN2B PGA" },
{ "MIXOUTR", "IN2B Switch", "IN2B PGA" },
};
static const struct snd_soc_dapm_route audio_map_in2_diff[] = {
{ "IN2A PGA", NULL, "IN2-" },
};
static int wm9090_add_controls(struct snd_soc_codec *codec)
{
struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec);
int i;
snd_soc_dapm_new_controls(codec, wm9090_dapm_widgets,
ARRAY_SIZE(wm9090_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_add_controls(codec, wm9090_controls,
ARRAY_SIZE(wm9090_controls));
if (wm9090->pdata.lin1_diff) {
snd_soc_dapm_add_routes(codec, audio_map_in1_diff,
ARRAY_SIZE(audio_map_in1_diff));
} else {
snd_soc_dapm_add_routes(codec, audio_map_in1_se,
ARRAY_SIZE(audio_map_in1_se));
snd_soc_add_controls(codec, wm9090_in1_se_controls,
ARRAY_SIZE(wm9090_in1_se_controls));
}
if (wm9090->pdata.lin2_diff) {
snd_soc_dapm_add_routes(codec, audio_map_in2_diff,
ARRAY_SIZE(audio_map_in2_diff));
} else {
snd_soc_dapm_add_routes(codec, audio_map_in2_se,
ARRAY_SIZE(audio_map_in2_se));
snd_soc_add_controls(codec, wm9090_in2_se_controls,
ARRAY_SIZE(wm9090_in2_se_controls));
}
if (wm9090->pdata.agc_ena) {
for (i = 0; i < ARRAY_SIZE(wm9090->pdata.agc); i++)
snd_soc_write(codec, WM9090_AGC_CONTROL_0 + i,
wm9090->pdata.agc[i]);
snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_3,
WM9090_AGC_ENA, WM9090_AGC_ENA);
} else {
snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_3,
WM9090_AGC_ENA, 0);
}
return 0;
}
/*
* The machine driver should call this from their set_bias_level; if there
* isn't one then this can just be set as the set_bias_level function.
*/
static int wm9090_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 *reg_cache = codec->reg_cache;
int i, ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_update_bits(codec, WM9090_ANTIPOP2, WM9090_VMID_ENA,
WM9090_VMID_ENA);
snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_1,
WM9090_BIAS_ENA |
WM9090_VMID_RES_MASK,
WM9090_BIAS_ENA |
1 << WM9090_VMID_RES_SHIFT);
msleep(1); /* Probably an overestimate */
break;
case SND_SOC_BIAS_STANDBY:
if (codec->bias_level == SND_SOC_BIAS_OFF) {
/* Restore the register cache */
for (i = 1; i < codec->reg_cache_size; i++) {
if (reg_cache[i] == wm9090_reg_defaults[i])
continue;
if (wm9090_volatile(i))
continue;
ret = snd_soc_write(codec, i, reg_cache[i]);
if (ret != 0)
dev_warn(codec->dev,
"Failed to restore register %d: %d\n",
i, ret);
}
}
/* We keep VMID off during standby since the combination of
* ground referenced outputs and class D speaker mean that
* latency is not an issue.
*/
snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_1,
WM9090_BIAS_ENA | WM9090_VMID_RES_MASK, 0);
snd_soc_update_bits(codec, WM9090_ANTIPOP2,
WM9090_VMID_ENA, 0);
break;
case SND_SOC_BIAS_OFF:
break;
}
codec->bias_level = level;
return 0;
}
static int wm9090_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (wm9090_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm9090_codec;
codec = wm9090_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
wm9090_add_controls(codec);
return 0;
pcm_err:
return ret;
}
#ifdef CONFIG_PM
static int wm9090_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm9090_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm9090_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
return 0;
}
#else
#define wm9090_suspend NULL
#define wm9090_resume NULL
#endif
static int wm9090_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm9090 = {
.probe = wm9090_probe,
.remove = wm9090_remove,
.suspend = wm9090_suspend,
.resume = wm9090_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm9090);
static int wm9090_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm9090_priv *wm9090;
struct snd_soc_codec *codec;
int ret;
wm9090 = kzalloc(sizeof(*wm9090), GFP_KERNEL);
if (wm9090 == NULL) {
dev_err(&i2c->dev, "Can not allocate memory\n");
return -ENOMEM;
}
codec = &wm9090->codec;
if (i2c->dev.platform_data)
memcpy(&wm9090->pdata, i2c->dev.platform_data,
sizeof(wm9090->pdata));
wm9090_codec = codec;
i2c_set_clientdata(i2c, wm9090);
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->control_data = i2c;
snd_soc_codec_set_drvdata(codec, wm9090);
codec->dev = &i2c->dev;
codec->name = "WM9090";
codec->owner = THIS_MODULE;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm9090_set_bias_level,
codec->reg_cache_size = WM9090_MAX_REGISTER + 1;
codec->reg_cache = &wm9090->reg_cache;
codec->volatile_register = wm9090_volatile;
ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
if (ret != 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
goto err;
}
memcpy(&wm9090->reg_cache, wm9090_reg_defaults,
sizeof(wm9090->reg_cache));
ret = snd_soc_read(codec, WM9090_SOFTWARE_RESET);
if (ret < 0)
goto err;
if (ret != wm9090_reg_defaults[WM9090_SOFTWARE_RESET]) {
dev_err(&i2c->dev, "Device is not a WM9090, ID=%x\n", ret);
ret = -EINVAL;
goto err;
}
ret = snd_soc_write(codec, WM9090_SOFTWARE_RESET, 0);
if (ret < 0)
goto err;
/* Configure some defaults; they will be written out when we
* bring the bias up.
*/
wm9090->reg_cache[WM9090_IN1_LINE_INPUT_A_VOLUME] |= WM9090_IN1_VU
| WM9090_IN1A_ZC;
wm9090->reg_cache[WM9090_IN1_LINE_INPUT_B_VOLUME] |= WM9090_IN1_VU
| WM9090_IN1B_ZC;
wm9090->reg_cache[WM9090_IN2_LINE_INPUT_A_VOLUME] |= WM9090_IN2_VU
| WM9090_IN2A_ZC;
wm9090->reg_cache[WM9090_IN2_LINE_INPUT_B_VOLUME] |= WM9090_IN2_VU
| WM9090_IN2B_ZC;
wm9090->reg_cache[WM9090_SPEAKER_VOLUME_LEFT] |=
WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC;
wm9090->reg_cache[WM9090_LEFT_OUTPUT_VOLUME] |=
WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC;
wm9090->reg_cache[WM9090_RIGHT_OUTPUT_VOLUME] |=
WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC;
wm9090->reg_cache[WM9090_CLOCKING_1] |= WM9090_TOCLK_ENA;
wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
goto err_bias;
}
return 0;
err_bias:
wm9090_set_bias_level(codec, SND_SOC_BIAS_OFF);
err:
kfree(wm9090);
i2c_set_clientdata(i2c, NULL);
wm9090_codec = NULL;
return ret;
}
static int wm9090_i2c_remove(struct i2c_client *i2c)
{
struct wm9090_priv *wm9090 = i2c_get_clientdata(i2c);
struct snd_soc_codec *codec = &wm9090->codec;
snd_soc_unregister_codec(codec);
wm9090_set_bias_level(codec, SND_SOC_BIAS_OFF);
kfree(wm9090);
wm9090_codec = NULL;
return 0;
}
static const struct i2c_device_id wm9090_id[] = {
{ "wm9090", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm9090_id);
static struct i2c_driver wm9090_i2c_driver = {
.driver = {
.name = "wm9090",
.owner = THIS_MODULE,
},
.probe = wm9090_i2c_probe,
.remove = __devexit_p(wm9090_i2c_remove),
.id_table = wm9090_id,
};
static int __init wm9090_init(void)
{
return i2c_add_driver(&wm9090_i2c_driver);
}
module_init(wm9090_init);
static void __exit wm9090_exit(void)
{
i2c_del_driver(&wm9090_i2c_driver);
}
module_exit(wm9090_exit);
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_DESCRIPTION("WM9090 ASoC driver");
MODULE_LICENSE("GPL");

715
sound/soc/codecs/wm9090.h Normal file
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@ -0,0 +1,715 @@
/*
* ALSA SoC WM9090 driver
*
* Copyright 2009 Wolfson Microelectronics
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef __WM9090_H
#define __WM9090_H
extern struct snd_soc_codec_device soc_codec_dev_wm9090;
/*
* Register values.
*/
#define WM9090_SOFTWARE_RESET 0x00
#define WM9090_POWER_MANAGEMENT_1 0x01
#define WM9090_POWER_MANAGEMENT_2 0x02
#define WM9090_POWER_MANAGEMENT_3 0x03
#define WM9090_CLOCKING_1 0x06
#define WM9090_IN1_LINE_CONTROL 0x16
#define WM9090_IN2_LINE_CONTROL 0x17
#define WM9090_IN1_LINE_INPUT_A_VOLUME 0x18
#define WM9090_IN1_LINE_INPUT_B_VOLUME 0x19
#define WM9090_IN2_LINE_INPUT_A_VOLUME 0x1A
#define WM9090_IN2_LINE_INPUT_B_VOLUME 0x1B
#define WM9090_LEFT_OUTPUT_VOLUME 0x1C
#define WM9090_RIGHT_OUTPUT_VOLUME 0x1D
#define WM9090_SPKMIXL_ATTENUATION 0x22
#define WM9090_SPKOUT_MIXERS 0x24
#define WM9090_CLASSD3 0x25
#define WM9090_SPEAKER_VOLUME_LEFT 0x26
#define WM9090_OUTPUT_MIXER1 0x2D
#define WM9090_OUTPUT_MIXER2 0x2E
#define WM9090_OUTPUT_MIXER3 0x2F
#define WM9090_OUTPUT_MIXER4 0x30
#define WM9090_SPEAKER_MIXER 0x36
#define WM9090_ANTIPOP2 0x39
#define WM9090_WRITE_SEQUENCER_0 0x46
#define WM9090_WRITE_SEQUENCER_1 0x47
#define WM9090_WRITE_SEQUENCER_2 0x48
#define WM9090_WRITE_SEQUENCER_3 0x49
#define WM9090_WRITE_SEQUENCER_4 0x4A
#define WM9090_WRITE_SEQUENCER_5 0x4B
#define WM9090_CHARGE_PUMP_1 0x4C
#define WM9090_DC_SERVO_0 0x54
#define WM9090_DC_SERVO_1 0x55
#define WM9090_DC_SERVO_3 0x57
#define WM9090_DC_SERVO_READBACK_0 0x58
#define WM9090_DC_SERVO_READBACK_1 0x59
#define WM9090_DC_SERVO_READBACK_2 0x5A
#define WM9090_ANALOGUE_HP_0 0x60
#define WM9090_AGC_CONTROL_0 0x62
#define WM9090_AGC_CONTROL_1 0x63
#define WM9090_AGC_CONTROL_2 0x64
#define WM9090_REGISTER_COUNT 40
#define WM9090_MAX_REGISTER 0x64
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Software Reset
*/
#define WM9090_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
#define WM9090_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
#define WM9090_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
/*
* R1 (0x01) - Power Management (1)
*/
#define WM9090_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */
#define WM9090_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */
#define WM9090_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */
#define WM9090_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */
#define WM9090_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */
#define WM9090_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */
#define WM9090_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */
#define WM9090_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
#define WM9090_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */
#define WM9090_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */
#define WM9090_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */
#define WM9090_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
#define WM9090_OSC_ENA 0x0008 /* OSC_ENA */
#define WM9090_OSC_ENA_MASK 0x0008 /* OSC_ENA */
#define WM9090_OSC_ENA_SHIFT 3 /* OSC_ENA */
#define WM9090_OSC_ENA_WIDTH 1 /* OSC_ENA */
#define WM9090_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */
#define WM9090_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */
#define WM9090_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */
#define WM9090_BIAS_ENA 0x0001 /* BIAS_ENA */
#define WM9090_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
#define WM9090_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
#define WM9090_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
/*
* R2 (0x02) - Power Management (2)
*/
#define WM9090_TSHUT 0x8000 /* TSHUT */
#define WM9090_TSHUT_MASK 0x8000 /* TSHUT */
#define WM9090_TSHUT_SHIFT 15 /* TSHUT */
#define WM9090_TSHUT_WIDTH 1 /* TSHUT */
#define WM9090_TSHUT_ENA 0x4000 /* TSHUT_ENA */
#define WM9090_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
#define WM9090_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
#define WM9090_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
#define WM9090_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
#define WM9090_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
#define WM9090_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
#define WM9090_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
#define WM9090_IN1A_ENA 0x0080 /* IN1A_ENA */
#define WM9090_IN1A_ENA_MASK 0x0080 /* IN1A_ENA */
#define WM9090_IN1A_ENA_SHIFT 7 /* IN1A_ENA */
#define WM9090_IN1A_ENA_WIDTH 1 /* IN1A_ENA */
#define WM9090_IN1B_ENA 0x0040 /* IN1B_ENA */
#define WM9090_IN1B_ENA_MASK 0x0040 /* IN1B_ENA */
#define WM9090_IN1B_ENA_SHIFT 6 /* IN1B_ENA */
#define WM9090_IN1B_ENA_WIDTH 1 /* IN1B_ENA */
#define WM9090_IN2A_ENA 0x0020 /* IN2A_ENA */
#define WM9090_IN2A_ENA_MASK 0x0020 /* IN2A_ENA */
#define WM9090_IN2A_ENA_SHIFT 5 /* IN2A_ENA */
#define WM9090_IN2A_ENA_WIDTH 1 /* IN2A_ENA */
#define WM9090_IN2B_ENA 0x0010 /* IN2B_ENA */
#define WM9090_IN2B_ENA_MASK 0x0010 /* IN2B_ENA */
#define WM9090_IN2B_ENA_SHIFT 4 /* IN2B_ENA */
#define WM9090_IN2B_ENA_WIDTH 1 /* IN2B_ENA */
/*
* R3 (0x03) - Power Management (3)
*/
#define WM9090_AGC_ENA 0x4000 /* AGC_ENA */
#define WM9090_AGC_ENA_MASK 0x4000 /* AGC_ENA */
#define WM9090_AGC_ENA_SHIFT 14 /* AGC_ENA */
#define WM9090_AGC_ENA_WIDTH 1 /* AGC_ENA */
#define WM9090_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */
#define WM9090_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */
#define WM9090_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */
#define WM9090_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */
#define WM9090_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */
#define WM9090_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */
#define WM9090_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */
#define WM9090_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */
#define WM9090_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */
#define WM9090_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */
#define WM9090_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */
#define WM9090_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */
#define WM9090_SPKMIX_ENA 0x0008 /* SPKMIX_ENA */
#define WM9090_SPKMIX_ENA_MASK 0x0008 /* SPKMIX_ENA */
#define WM9090_SPKMIX_ENA_SHIFT 3 /* SPKMIX_ENA */
#define WM9090_SPKMIX_ENA_WIDTH 1 /* SPKMIX_ENA */
/*
* R6 (0x06) - Clocking 1
*/
#define WM9090_TOCLK_RATE 0x8000 /* TOCLK_RATE */
#define WM9090_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */
#define WM9090_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */
#define WM9090_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */
#define WM9090_TOCLK_ENA 0x4000 /* TOCLK_ENA */
#define WM9090_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */
#define WM9090_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */
#define WM9090_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
/*
* R22 (0x16) - IN1 Line Control
*/
#define WM9090_IN1_DIFF 0x0002 /* IN1_DIFF */
#define WM9090_IN1_DIFF_MASK 0x0002 /* IN1_DIFF */
#define WM9090_IN1_DIFF_SHIFT 1 /* IN1_DIFF */
#define WM9090_IN1_DIFF_WIDTH 1 /* IN1_DIFF */
#define WM9090_IN1_CLAMP 0x0001 /* IN1_CLAMP */
#define WM9090_IN1_CLAMP_MASK 0x0001 /* IN1_CLAMP */
#define WM9090_IN1_CLAMP_SHIFT 0 /* IN1_CLAMP */
#define WM9090_IN1_CLAMP_WIDTH 1 /* IN1_CLAMP */
/*
* R23 (0x17) - IN2 Line Control
*/
#define WM9090_IN2_DIFF 0x0002 /* IN2_DIFF */
#define WM9090_IN2_DIFF_MASK 0x0002 /* IN2_DIFF */
#define WM9090_IN2_DIFF_SHIFT 1 /* IN2_DIFF */
#define WM9090_IN2_DIFF_WIDTH 1 /* IN2_DIFF */
#define WM9090_IN2_CLAMP 0x0001 /* IN2_CLAMP */
#define WM9090_IN2_CLAMP_MASK 0x0001 /* IN2_CLAMP */
#define WM9090_IN2_CLAMP_SHIFT 0 /* IN2_CLAMP */
#define WM9090_IN2_CLAMP_WIDTH 1 /* IN2_CLAMP */
/*
* R24 (0x18) - IN1 Line Input A Volume
*/
#define WM9090_IN1_VU 0x0100 /* IN1_VU */
#define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */
#define WM9090_IN1_VU_SHIFT 8 /* IN1_VU */
#define WM9090_IN1_VU_WIDTH 1 /* IN1_VU */
#define WM9090_IN1A_MUTE 0x0080 /* IN1A_MUTE */
#define WM9090_IN1A_MUTE_MASK 0x0080 /* IN1A_MUTE */
#define WM9090_IN1A_MUTE_SHIFT 7 /* IN1A_MUTE */
#define WM9090_IN1A_MUTE_WIDTH 1 /* IN1A_MUTE */
#define WM9090_IN1A_ZC 0x0040 /* IN1A_ZC */
#define WM9090_IN1A_ZC_MASK 0x0040 /* IN1A_ZC */
#define WM9090_IN1A_ZC_SHIFT 6 /* IN1A_ZC */
#define WM9090_IN1A_ZC_WIDTH 1 /* IN1A_ZC */
#define WM9090_IN1A_VOL_MASK 0x0007 /* IN1A_VOL - [2:0] */
#define WM9090_IN1A_VOL_SHIFT 0 /* IN1A_VOL - [2:0] */
#define WM9090_IN1A_VOL_WIDTH 3 /* IN1A_VOL - [2:0] */
/*
* R25 (0x19) - IN1 Line Input B Volume
*/
#define WM9090_IN1_VU 0x0100 /* IN1_VU */
#define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */
#define WM9090_IN1_VU_SHIFT 8 /* IN1_VU */
#define WM9090_IN1_VU_WIDTH 1 /* IN1_VU */
#define WM9090_IN1B_MUTE 0x0080 /* IN1B_MUTE */
#define WM9090_IN1B_MUTE_MASK 0x0080 /* IN1B_MUTE */
#define WM9090_IN1B_MUTE_SHIFT 7 /* IN1B_MUTE */
#define WM9090_IN1B_MUTE_WIDTH 1 /* IN1B_MUTE */
#define WM9090_IN1B_ZC 0x0040 /* IN1B_ZC */
#define WM9090_IN1B_ZC_MASK 0x0040 /* IN1B_ZC */
#define WM9090_IN1B_ZC_SHIFT 6 /* IN1B_ZC */
#define WM9090_IN1B_ZC_WIDTH 1 /* IN1B_ZC */
#define WM9090_IN1B_VOL_MASK 0x0007 /* IN1B_VOL - [2:0] */
#define WM9090_IN1B_VOL_SHIFT 0 /* IN1B_VOL - [2:0] */
#define WM9090_IN1B_VOL_WIDTH 3 /* IN1B_VOL - [2:0] */
/*
* R26 (0x1A) - IN2 Line Input A Volume
*/
#define WM9090_IN2_VU 0x0100 /* IN2_VU */
#define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */
#define WM9090_IN2_VU_SHIFT 8 /* IN2_VU */
#define WM9090_IN2_VU_WIDTH 1 /* IN2_VU */
#define WM9090_IN2A_MUTE 0x0080 /* IN2A_MUTE */
#define WM9090_IN2A_MUTE_MASK 0x0080 /* IN2A_MUTE */
#define WM9090_IN2A_MUTE_SHIFT 7 /* IN2A_MUTE */
#define WM9090_IN2A_MUTE_WIDTH 1 /* IN2A_MUTE */
#define WM9090_IN2A_ZC 0x0040 /* IN2A_ZC */
#define WM9090_IN2A_ZC_MASK 0x0040 /* IN2A_ZC */
#define WM9090_IN2A_ZC_SHIFT 6 /* IN2A_ZC */
#define WM9090_IN2A_ZC_WIDTH 1 /* IN2A_ZC */
#define WM9090_IN2A_VOL_MASK 0x0007 /* IN2A_VOL - [2:0] */
#define WM9090_IN2A_VOL_SHIFT 0 /* IN2A_VOL - [2:0] */
#define WM9090_IN2A_VOL_WIDTH 3 /* IN2A_VOL - [2:0] */
/*
* R27 (0x1B) - IN2 Line Input B Volume
*/
#define WM9090_IN2_VU 0x0100 /* IN2_VU */
#define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */
#define WM9090_IN2_VU_SHIFT 8 /* IN2_VU */
#define WM9090_IN2_VU_WIDTH 1 /* IN2_VU */
#define WM9090_IN2B_MUTE 0x0080 /* IN2B_MUTE */
#define WM9090_IN2B_MUTE_MASK 0x0080 /* IN2B_MUTE */
#define WM9090_IN2B_MUTE_SHIFT 7 /* IN2B_MUTE */
#define WM9090_IN2B_MUTE_WIDTH 1 /* IN2B_MUTE */
#define WM9090_IN2B_ZC 0x0040 /* IN2B_ZC */
#define WM9090_IN2B_ZC_MASK 0x0040 /* IN2B_ZC */
#define WM9090_IN2B_ZC_SHIFT 6 /* IN2B_ZC */
#define WM9090_IN2B_ZC_WIDTH 1 /* IN2B_ZC */
#define WM9090_IN2B_VOL_MASK 0x0007 /* IN2B_VOL - [2:0] */
#define WM9090_IN2B_VOL_SHIFT 0 /* IN2B_VOL - [2:0] */
#define WM9090_IN2B_VOL_WIDTH 3 /* IN2B_VOL - [2:0] */
/*
* R28 (0x1C) - Left Output Volume
*/
#define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */
#define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
#define WM9090_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
#define WM9090_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
#define WM9090_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
#define WM9090_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
#define WM9090_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */
#define WM9090_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
#define WM9090_HPOUT1L_MUTE 0x0040 /* HPOUT1L_MUTE */
#define WM9090_HPOUT1L_MUTE_MASK 0x0040 /* HPOUT1L_MUTE */
#define WM9090_HPOUT1L_MUTE_SHIFT 6 /* HPOUT1L_MUTE */
#define WM9090_HPOUT1L_MUTE_WIDTH 1 /* HPOUT1L_MUTE */
#define WM9090_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */
#define WM9090_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */
#define WM9090_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */
/*
* R29 (0x1D) - Right Output Volume
*/
#define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */
#define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
#define WM9090_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
#define WM9090_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
#define WM9090_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
#define WM9090_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
#define WM9090_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */
#define WM9090_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
#define WM9090_HPOUT1R_MUTE 0x0040 /* HPOUT1R_MUTE */
#define WM9090_HPOUT1R_MUTE_MASK 0x0040 /* HPOUT1R_MUTE */
#define WM9090_HPOUT1R_MUTE_SHIFT 6 /* HPOUT1R_MUTE */
#define WM9090_HPOUT1R_MUTE_WIDTH 1 /* HPOUT1R_MUTE */
#define WM9090_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */
#define WM9090_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */
#define WM9090_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */
/*
* R34 (0x22) - SPKMIXL Attenuation
*/
#define WM9090_SPKMIX_MUTE 0x0100 /* SPKMIX_MUTE */
#define WM9090_SPKMIX_MUTE_MASK 0x0100 /* SPKMIX_MUTE */
#define WM9090_SPKMIX_MUTE_SHIFT 8 /* SPKMIX_MUTE */
#define WM9090_SPKMIX_MUTE_WIDTH 1 /* SPKMIX_MUTE */
#define WM9090_IN1A_SPKMIX_VOL_MASK 0x00C0 /* IN1A_SPKMIX_VOL - [7:6] */
#define WM9090_IN1A_SPKMIX_VOL_SHIFT 6 /* IN1A_SPKMIX_VOL - [7:6] */
#define WM9090_IN1A_SPKMIX_VOL_WIDTH 2 /* IN1A_SPKMIX_VOL - [7:6] */
#define WM9090_IN1B_SPKMIX_VOL_MASK 0x0030 /* IN1B_SPKMIX_VOL - [5:4] */
#define WM9090_IN1B_SPKMIX_VOL_SHIFT 4 /* IN1B_SPKMIX_VOL - [5:4] */
#define WM9090_IN1B_SPKMIX_VOL_WIDTH 2 /* IN1B_SPKMIX_VOL - [5:4] */
#define WM9090_IN2A_SPKMIX_VOL_MASK 0x000C /* IN2A_SPKMIX_VOL - [3:2] */
#define WM9090_IN2A_SPKMIX_VOL_SHIFT 2 /* IN2A_SPKMIX_VOL - [3:2] */
#define WM9090_IN2A_SPKMIX_VOL_WIDTH 2 /* IN2A_SPKMIX_VOL - [3:2] */
#define WM9090_IN2B_SPKMIX_VOL_MASK 0x0003 /* IN2B_SPKMIX_VOL - [1:0] */
#define WM9090_IN2B_SPKMIX_VOL_SHIFT 0 /* IN2B_SPKMIX_VOL - [1:0] */
#define WM9090_IN2B_SPKMIX_VOL_WIDTH 2 /* IN2B_SPKMIX_VOL - [1:0] */
/*
* R36 (0x24) - SPKOUT Mixers
*/
#define WM9090_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */
#define WM9090_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */
#define WM9090_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */
#define WM9090_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */
/*
* R37 (0x25) - ClassD3
*/
#define WM9090_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */
#define WM9090_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */
#define WM9090_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */
/*
* R38 (0x26) - Speaker Volume Left
*/
#define WM9090_SPKOUT_VU 0x0100 /* SPKOUT_VU */
#define WM9090_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
#define WM9090_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
#define WM9090_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
#define WM9090_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */
#define WM9090_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */
#define WM9090_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */
#define WM9090_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */
#define WM9090_SPKOUTL_MUTE 0x0040 /* SPKOUTL_MUTE */
#define WM9090_SPKOUTL_MUTE_MASK 0x0040 /* SPKOUTL_MUTE */
#define WM9090_SPKOUTL_MUTE_SHIFT 6 /* SPKOUTL_MUTE */
#define WM9090_SPKOUTL_MUTE_WIDTH 1 /* SPKOUTL_MUTE */
#define WM9090_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */
#define WM9090_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */
#define WM9090_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */
/*
* R45 (0x2D) - Output Mixer1
*/
#define WM9090_IN1A_TO_MIXOUTL 0x0040 /* IN1A_TO_MIXOUTL */
#define WM9090_IN1A_TO_MIXOUTL_MASK 0x0040 /* IN1A_TO_MIXOUTL */
#define WM9090_IN1A_TO_MIXOUTL_SHIFT 6 /* IN1A_TO_MIXOUTL */
#define WM9090_IN1A_TO_MIXOUTL_WIDTH 1 /* IN1A_TO_MIXOUTL */
#define WM9090_IN2A_TO_MIXOUTL 0x0004 /* IN2A_TO_MIXOUTL */
#define WM9090_IN2A_TO_MIXOUTL_MASK 0x0004 /* IN2A_TO_MIXOUTL */
#define WM9090_IN2A_TO_MIXOUTL_SHIFT 2 /* IN2A_TO_MIXOUTL */
#define WM9090_IN2A_TO_MIXOUTL_WIDTH 1 /* IN2A_TO_MIXOUTL */
/*
* R46 (0x2E) - Output Mixer2
*/
#define WM9090_IN1A_TO_MIXOUTR 0x0040 /* IN1A_TO_MIXOUTR */
#define WM9090_IN1A_TO_MIXOUTR_MASK 0x0040 /* IN1A_TO_MIXOUTR */
#define WM9090_IN1A_TO_MIXOUTR_SHIFT 6 /* IN1A_TO_MIXOUTR */
#define WM9090_IN1A_TO_MIXOUTR_WIDTH 1 /* IN1A_TO_MIXOUTR */
#define WM9090_IN1B_TO_MIXOUTR 0x0010 /* IN1B_TO_MIXOUTR */
#define WM9090_IN1B_TO_MIXOUTR_MASK 0x0010 /* IN1B_TO_MIXOUTR */
#define WM9090_IN1B_TO_MIXOUTR_SHIFT 4 /* IN1B_TO_MIXOUTR */
#define WM9090_IN1B_TO_MIXOUTR_WIDTH 1 /* IN1B_TO_MIXOUTR */
#define WM9090_IN2A_TO_MIXOUTR 0x0004 /* IN2A_TO_MIXOUTR */
#define WM9090_IN2A_TO_MIXOUTR_MASK 0x0004 /* IN2A_TO_MIXOUTR */
#define WM9090_IN2A_TO_MIXOUTR_SHIFT 2 /* IN2A_TO_MIXOUTR */
#define WM9090_IN2A_TO_MIXOUTR_WIDTH 1 /* IN2A_TO_MIXOUTR */
#define WM9090_IN2B_TO_MIXOUTR 0x0001 /* IN2B_TO_MIXOUTR */
#define WM9090_IN2B_TO_MIXOUTR_MASK 0x0001 /* IN2B_TO_MIXOUTR */
#define WM9090_IN2B_TO_MIXOUTR_SHIFT 0 /* IN2B_TO_MIXOUTR */
#define WM9090_IN2B_TO_MIXOUTR_WIDTH 1 /* IN2B_TO_MIXOUTR */
/*
* R47 (0x2F) - Output Mixer3
*/
#define WM9090_MIXOUTL_MUTE 0x0100 /* MIXOUTL_MUTE */
#define WM9090_MIXOUTL_MUTE_MASK 0x0100 /* MIXOUTL_MUTE */
#define WM9090_MIXOUTL_MUTE_SHIFT 8 /* MIXOUTL_MUTE */
#define WM9090_MIXOUTL_MUTE_WIDTH 1 /* MIXOUTL_MUTE */
#define WM9090_IN1A_MIXOUTL_VOL_MASK 0x00C0 /* IN1A_MIXOUTL_VOL - [7:6] */
#define WM9090_IN1A_MIXOUTL_VOL_SHIFT 6 /* IN1A_MIXOUTL_VOL - [7:6] */
#define WM9090_IN1A_MIXOUTL_VOL_WIDTH 2 /* IN1A_MIXOUTL_VOL - [7:6] */
#define WM9090_IN2A_MIXOUTL_VOL_MASK 0x000C /* IN2A_MIXOUTL_VOL - [3:2] */
#define WM9090_IN2A_MIXOUTL_VOL_SHIFT 2 /* IN2A_MIXOUTL_VOL - [3:2] */
#define WM9090_IN2A_MIXOUTL_VOL_WIDTH 2 /* IN2A_MIXOUTL_VOL - [3:2] */
/*
* R48 (0x30) - Output Mixer4
*/
#define WM9090_MIXOUTR_MUTE 0x0100 /* MIXOUTR_MUTE */
#define WM9090_MIXOUTR_MUTE_MASK 0x0100 /* MIXOUTR_MUTE */
#define WM9090_MIXOUTR_MUTE_SHIFT 8 /* MIXOUTR_MUTE */
#define WM9090_MIXOUTR_MUTE_WIDTH 1 /* MIXOUTR_MUTE */
#define WM9090_IN1A_MIXOUTR_VOL_MASK 0x00C0 /* IN1A_MIXOUTR_VOL - [7:6] */
#define WM9090_IN1A_MIXOUTR_VOL_SHIFT 6 /* IN1A_MIXOUTR_VOL - [7:6] */
#define WM9090_IN1A_MIXOUTR_VOL_WIDTH 2 /* IN1A_MIXOUTR_VOL - [7:6] */
#define WM9090_IN1B_MIXOUTR_VOL_MASK 0x0030 /* IN1B_MIXOUTR_VOL - [5:4] */
#define WM9090_IN1B_MIXOUTR_VOL_SHIFT 4 /* IN1B_MIXOUTR_VOL - [5:4] */
#define WM9090_IN1B_MIXOUTR_VOL_WIDTH 2 /* IN1B_MIXOUTR_VOL - [5:4] */
#define WM9090_IN2A_MIXOUTR_VOL_MASK 0x000C /* IN2A_MIXOUTR_VOL - [3:2] */
#define WM9090_IN2A_MIXOUTR_VOL_SHIFT 2 /* IN2A_MIXOUTR_VOL - [3:2] */
#define WM9090_IN2A_MIXOUTR_VOL_WIDTH 2 /* IN2A_MIXOUTR_VOL - [3:2] */
#define WM9090_IN2B_MIXOUTR_VOL_MASK 0x0003 /* IN2B_MIXOUTR_VOL - [1:0] */
#define WM9090_IN2B_MIXOUTR_VOL_SHIFT 0 /* IN2B_MIXOUTR_VOL - [1:0] */
#define WM9090_IN2B_MIXOUTR_VOL_WIDTH 2 /* IN2B_MIXOUTR_VOL - [1:0] */
/*
* R54 (0x36) - Speaker Mixer
*/
#define WM9090_IN1A_TO_SPKMIX 0x0040 /* IN1A_TO_SPKMIX */
#define WM9090_IN1A_TO_SPKMIX_MASK 0x0040 /* IN1A_TO_SPKMIX */
#define WM9090_IN1A_TO_SPKMIX_SHIFT 6 /* IN1A_TO_SPKMIX */
#define WM9090_IN1A_TO_SPKMIX_WIDTH 1 /* IN1A_TO_SPKMIX */
#define WM9090_IN1B_TO_SPKMIX 0x0010 /* IN1B_TO_SPKMIX */
#define WM9090_IN1B_TO_SPKMIX_MASK 0x0010 /* IN1B_TO_SPKMIX */
#define WM9090_IN1B_TO_SPKMIX_SHIFT 4 /* IN1B_TO_SPKMIX */
#define WM9090_IN1B_TO_SPKMIX_WIDTH 1 /* IN1B_TO_SPKMIX */
#define WM9090_IN2A_TO_SPKMIX 0x0004 /* IN2A_TO_SPKMIX */
#define WM9090_IN2A_TO_SPKMIX_MASK 0x0004 /* IN2A_TO_SPKMIX */
#define WM9090_IN2A_TO_SPKMIX_SHIFT 2 /* IN2A_TO_SPKMIX */
#define WM9090_IN2A_TO_SPKMIX_WIDTH 1 /* IN2A_TO_SPKMIX */
#define WM9090_IN2B_TO_SPKMIX 0x0001 /* IN2B_TO_SPKMIX */
#define WM9090_IN2B_TO_SPKMIX_MASK 0x0001 /* IN2B_TO_SPKMIX */
#define WM9090_IN2B_TO_SPKMIX_SHIFT 0 /* IN2B_TO_SPKMIX */
#define WM9090_IN2B_TO_SPKMIX_WIDTH 1 /* IN2B_TO_SPKMIX */
/*
* R57 (0x39) - AntiPOP2
*/
#define WM9090_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */
#define WM9090_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */
#define WM9090_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */
#define WM9090_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
#define WM9090_VMID_ENA 0x0001 /* VMID_ENA */
#define WM9090_VMID_ENA_MASK 0x0001 /* VMID_ENA */
#define WM9090_VMID_ENA_SHIFT 0 /* VMID_ENA */
#define WM9090_VMID_ENA_WIDTH 1 /* VMID_ENA */
/*
* R70 (0x46) - Write Sequencer 0
*/
#define WM9090_WSEQ_ENA 0x0100 /* WSEQ_ENA */
#define WM9090_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */
#define WM9090_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */
#define WM9090_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
#define WM9090_WSEQ_WRITE_INDEX_MASK 0x000F /* WSEQ_WRITE_INDEX - [3:0] */
#define WM9090_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [3:0] */
#define WM9090_WSEQ_WRITE_INDEX_WIDTH 4 /* WSEQ_WRITE_INDEX - [3:0] */
/*
* R71 (0x47) - Write Sequencer 1
*/
#define WM9090_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */
#define WM9090_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */
#define WM9090_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */
#define WM9090_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */
#define WM9090_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */
#define WM9090_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */
#define WM9090_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
#define WM9090_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
#define WM9090_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
/*
* R72 (0x48) - Write Sequencer 2
*/
#define WM9090_WSEQ_EOS 0x4000 /* WSEQ_EOS */
#define WM9090_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */
#define WM9090_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */
#define WM9090_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */
#define WM9090_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */
#define WM9090_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */
#define WM9090_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */
#define WM9090_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
#define WM9090_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
#define WM9090_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
/*
* R73 (0x49) - Write Sequencer 3
*/
#define WM9090_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
#define WM9090_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
#define WM9090_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
#define WM9090_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
#define WM9090_WSEQ_START 0x0100 /* WSEQ_START */
#define WM9090_WSEQ_START_MASK 0x0100 /* WSEQ_START */
#define WM9090_WSEQ_START_SHIFT 8 /* WSEQ_START */
#define WM9090_WSEQ_START_WIDTH 1 /* WSEQ_START */
#define WM9090_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
#define WM9090_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
#define WM9090_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
/*
* R74 (0x4A) - Write Sequencer 4
*/
#define WM9090_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
#define WM9090_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
#define WM9090_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
#define WM9090_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
/*
* R75 (0x4B) - Write Sequencer 5
*/
#define WM9090_WSEQ_CURRENT_INDEX_MASK 0x003F /* WSEQ_CURRENT_INDEX - [5:0] */
#define WM9090_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [5:0] */
#define WM9090_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [5:0] */
/*
* R76 (0x4C) - Charge Pump 1
*/
#define WM9090_CP_ENA 0x8000 /* CP_ENA */
#define WM9090_CP_ENA_MASK 0x8000 /* CP_ENA */
#define WM9090_CP_ENA_SHIFT 15 /* CP_ENA */
#define WM9090_CP_ENA_WIDTH 1 /* CP_ENA */
/*
* R84 (0x54) - DC Servo 0
*/
#define WM9090_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
#define WM9090_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
#define WM9090_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
#define WM9090_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
#define WM9090_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
#define WM9090_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
#define WM9090_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
#define WM9090_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
#define WM9090_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
#define WM9090_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
#define WM9090_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
#define WM9090_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
#define WM9090_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
#define WM9090_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
#define WM9090_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
#define WM9090_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
#define WM9090_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
#define WM9090_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
#define WM9090_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
#define WM9090_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
#define WM9090_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
#define WM9090_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
#define WM9090_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
#define WM9090_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
#define WM9090_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */
#define WM9090_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */
#define WM9090_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */
#define WM9090_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
#define WM9090_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */
#define WM9090_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */
#define WM9090_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */
#define WM9090_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
#define WM9090_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
#define WM9090_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
#define WM9090_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
#define WM9090_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
#define WM9090_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
#define WM9090_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
#define WM9090_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
#define WM9090_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
/*
* R85 (0x55) - DC Servo 1
*/
#define WM9090_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */
#define WM9090_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */
#define WM9090_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */
#define WM9090_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
#define WM9090_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
#define WM9090_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
/*
* R87 (0x57) - DC Servo 3
*/
#define WM9090_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
#define WM9090_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
#define WM9090_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
#define WM9090_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
#define WM9090_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
#define WM9090_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
/*
* R88 (0x58) - DC Servo Readback 0
*/
#define WM9090_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */
#define WM9090_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */
#define WM9090_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */
#define WM9090_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */
#define WM9090_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */
#define WM9090_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */
#define WM9090_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */
#define WM9090_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */
#define WM9090_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */
/*
* R89 (0x59) - DC Servo Readback 1
*/
#define WM9090_DCS_DAC_WR_VAL_1_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_1_RD - [7:0] */
#define WM9090_DCS_DAC_WR_VAL_1_RD_SHIFT 0 /* DCS_DAC_WR_VAL_1_RD - [7:0] */
#define WM9090_DCS_DAC_WR_VAL_1_RD_WIDTH 8 /* DCS_DAC_WR_VAL_1_RD - [7:0] */
/*
* R90 (0x5A) - DC Servo Readback 2
*/
#define WM9090_DCS_DAC_WR_VAL_0_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_0_RD - [7:0] */
#define WM9090_DCS_DAC_WR_VAL_0_RD_SHIFT 0 /* DCS_DAC_WR_VAL_0_RD - [7:0] */
#define WM9090_DCS_DAC_WR_VAL_0_RD_WIDTH 8 /* DCS_DAC_WR_VAL_0_RD - [7:0] */
/*
* R96 (0x60) - Analogue HP 0
*/
#define WM9090_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
#define WM9090_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
#define WM9090_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
#define WM9090_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
#define WM9090_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
#define WM9090_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
#define WM9090_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
#define WM9090_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
#define WM9090_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
#define WM9090_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
#define WM9090_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
#define WM9090_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
#define WM9090_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
#define WM9090_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
#define WM9090_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
#define WM9090_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
#define WM9090_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
#define WM9090_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
#define WM9090_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
#define WM9090_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
#define WM9090_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
#define WM9090_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
#define WM9090_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
#define WM9090_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
/*
* R98 (0x62) - AGC Control 0
*/
#define WM9090_AGC_CLIP_ENA 0x8000 /* AGC_CLIP_ENA */
#define WM9090_AGC_CLIP_ENA_MASK 0x8000 /* AGC_CLIP_ENA */
#define WM9090_AGC_CLIP_ENA_SHIFT 15 /* AGC_CLIP_ENA */
#define WM9090_AGC_CLIP_ENA_WIDTH 1 /* AGC_CLIP_ENA */
#define WM9090_AGC_CLIP_THR_MASK 0x0F00 /* AGC_CLIP_THR - [11:8] */
#define WM9090_AGC_CLIP_THR_SHIFT 8 /* AGC_CLIP_THR - [11:8] */
#define WM9090_AGC_CLIP_THR_WIDTH 4 /* AGC_CLIP_THR - [11:8] */
#define WM9090_AGC_CLIP_ATK_MASK 0x0070 /* AGC_CLIP_ATK - [6:4] */
#define WM9090_AGC_CLIP_ATK_SHIFT 4 /* AGC_CLIP_ATK - [6:4] */
#define WM9090_AGC_CLIP_ATK_WIDTH 3 /* AGC_CLIP_ATK - [6:4] */
#define WM9090_AGC_CLIP_DCY_MASK 0x0007 /* AGC_CLIP_DCY - [2:0] */
#define WM9090_AGC_CLIP_DCY_SHIFT 0 /* AGC_CLIP_DCY - [2:0] */
#define WM9090_AGC_CLIP_DCY_WIDTH 3 /* AGC_CLIP_DCY - [2:0] */
/*
* R99 (0x63) - AGC Control 1
*/
#define WM9090_AGC_PWR_ENA 0x8000 /* AGC_PWR_ENA */
#define WM9090_AGC_PWR_ENA_MASK 0x8000 /* AGC_PWR_ENA */
#define WM9090_AGC_PWR_ENA_SHIFT 15 /* AGC_PWR_ENA */
#define WM9090_AGC_PWR_ENA_WIDTH 1 /* AGC_PWR_ENA */
#define WM9090_AGC_PWR_AVG 0x1000 /* AGC_PWR_AVG */
#define WM9090_AGC_PWR_AVG_MASK 0x1000 /* AGC_PWR_AVG */
#define WM9090_AGC_PWR_AVG_SHIFT 12 /* AGC_PWR_AVG */
#define WM9090_AGC_PWR_AVG_WIDTH 1 /* AGC_PWR_AVG */
#define WM9090_AGC_PWR_THR_MASK 0x0F00 /* AGC_PWR_THR - [11:8] */
#define WM9090_AGC_PWR_THR_SHIFT 8 /* AGC_PWR_THR - [11:8] */
#define WM9090_AGC_PWR_THR_WIDTH 4 /* AGC_PWR_THR - [11:8] */
#define WM9090_AGC_PWR_ATK_MASK 0x0070 /* AGC_PWR_ATK - [6:4] */
#define WM9090_AGC_PWR_ATK_SHIFT 4 /* AGC_PWR_ATK - [6:4] */
#define WM9090_AGC_PWR_ATK_WIDTH 3 /* AGC_PWR_ATK - [6:4] */
#define WM9090_AGC_PWR_DCY_MASK 0x0007 /* AGC_PWR_DCY - [2:0] */
#define WM9090_AGC_PWR_DCY_SHIFT 0 /* AGC_PWR_DCY - [2:0] */
#define WM9090_AGC_PWR_DCY_WIDTH 3 /* AGC_PWR_DCY - [2:0] */
/*
* R100 (0x64) - AGC Control 2
*/
#define WM9090_AGC_RAMP 0x0100 /* AGC_RAMP */
#define WM9090_AGC_RAMP_MASK 0x0100 /* AGC_RAMP */
#define WM9090_AGC_RAMP_SHIFT 8 /* AGC_RAMP */
#define WM9090_AGC_RAMP_WIDTH 1 /* AGC_RAMP */
#define WM9090_AGC_MINGAIN_MASK 0x003F /* AGC_MINGAIN - [5:0] */
#define WM9090_AGC_MINGAIN_SHIFT 0 /* AGC_MINGAIN - [5:0] */
#define WM9090_AGC_MINGAIN_WIDTH 6 /* AGC_MINGAIN - [5:0] */
#endif