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arm: zynq: dt: Set correct L2 ram latencies

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Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Soren Brinkmann 2013-07-31 16:24:59 -07:00 committed by Michal Simek
parent d4e4ab86bc
commit 39c41df9c1
1 changed files with 2 additions and 2 deletions
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4
arch/arm/boot/dts/zynq-7000.dtsi
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@ -41,8 +41,8 @@
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
arm,data-latency = <2 3 2>;
arm,tag-latency = <2 3 2>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};