ASoC: OMAP: Add DSP_A mode support for mcbsp

DSP_A mode is similar to the DSP_B, but the MSB is delayed with
one bclk (appears after the FS pulse and not under it).

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Peter Ujfalusi 2009-04-15 15:38:56 +03:00 committed by Mark Brown
parent c29b206ffd
commit 3ba191ce05

View File

@ -287,6 +287,7 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
regs->srgr2 |= FPER(wlen * channels - 1); regs->srgr2 |= FPER(wlen * channels - 1);
regs->srgr1 |= FWID(wlen - 1); regs->srgr1 |= FWID(wlen - 1);
break; break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B: case SND_SOC_DAIFMT_DSP_B:
regs->srgr2 |= FPER(wlen * channels - 1); regs->srgr2 |= FPER(wlen * channels - 1);
regs->srgr1 |= FWID(wlen * channels - 2); regs->srgr1 |= FWID(wlen * channels - 2);
@ -330,6 +331,13 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
regs->rcr2 |= RDATDLY(1); regs->rcr2 |= RDATDLY(1);
regs->xcr2 |= XDATDLY(1); regs->xcr2 |= XDATDLY(1);
break; break;
case SND_SOC_DAIFMT_DSP_A:
/* 1-bit data delay */
regs->rcr2 |= RDATDLY(1);
regs->xcr2 |= XDATDLY(1);
/* Invert FS polarity configuration */
temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
break;
case SND_SOC_DAIFMT_DSP_B: case SND_SOC_DAIFMT_DSP_B:
/* 0-bit data delay */ /* 0-bit data delay */
regs->rcr2 |= RDATDLY(0); regs->rcr2 |= RDATDLY(0);