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amd-iommu: introduce for_each_iommu* macros
This patch introduces the for_each_iommu and for_each_iommu_safe macros to simplify the developers life when having to iterate over all AMD IOMMUs in the system. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -195,6 +195,14 @@
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#define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
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domain for an IOMMU */
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/*
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* Make iterating over all IOMMUs easier
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*/
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#define for_each_iommu(iommu) \
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list_for_each_entry((iommu), &amd_iommu_list, list)
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#define for_each_iommu_safe(iommu, next) \
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list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
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/*
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* This structure contains generic data for IOMMU protection domains
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* independent of their use.
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@ -213,7 +213,7 @@ irqreturn_t amd_iommu_int_handler(int irq, void *data)
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{
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struct amd_iommu *iommu;
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list_for_each_entry(iommu, &amd_iommu_list, list)
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for_each_iommu(iommu)
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iommu_poll_events(iommu);
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return IRQ_HANDLED;
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@ -440,7 +440,7 @@ static void iommu_flush_domain(u16 domid)
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__iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
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domid, 1, 1);
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list_for_each_entry(iommu, &amd_iommu_list, list) {
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for_each_iommu(iommu) {
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spin_lock_irqsave(&iommu->lock, flags);
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__iommu_queue_command(iommu, &cmd);
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__iommu_completion_wait(iommu);
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@ -1672,7 +1672,7 @@ int __init amd_iommu_init_dma_ops(void)
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* found in the system. Devices not assigned to any other
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* protection domain will be assigned to the default one.
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*/
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list_for_each_entry(iommu, &amd_iommu_list, list) {
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for_each_iommu(iommu) {
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iommu->default_dom = dma_ops_domain_alloc(iommu, order);
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if (iommu->default_dom == NULL)
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return -ENOMEM;
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@ -1710,7 +1710,7 @@ int __init amd_iommu_init_dma_ops(void)
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free_domains:
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list_for_each_entry(iommu, &amd_iommu_list, list) {
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for_each_iommu(iommu) {
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if (iommu->default_dom)
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dma_ops_domain_free(iommu->default_dom);
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}
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@ -679,7 +679,7 @@ static void __init free_iommu_all(void)
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{
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struct amd_iommu *iommu, *next;
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list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
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for_each_iommu_safe(iommu, next) {
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list_del(&iommu->list);
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free_iommu_one(iommu);
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kfree(iommu);
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@ -779,7 +779,7 @@ static int __init iommu_setup_msix(struct amd_iommu *iommu)
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struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */
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int nvec = 0, i;
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list_for_each_entry(curr, &amd_iommu_list, list) {
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for_each_iommu(curr) {
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if (curr->dev == iommu->dev) {
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entries[nvec].entry = curr->evt_msi_num;
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entries[nvec].vector = 0;
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@ -818,7 +818,7 @@ static int __init iommu_setup_msi(struct amd_iommu *iommu)
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int r;
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struct amd_iommu *curr;
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list_for_each_entry(curr, &amd_iommu_list, list) {
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for_each_iommu(curr) {
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if (curr->dev == iommu->dev)
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curr->int_enabled = true;
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}
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@ -971,7 +971,7 @@ static void __init enable_iommus(void)
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{
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struct amd_iommu *iommu;
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list_for_each_entry(iommu, &amd_iommu_list, list) {
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for_each_iommu(iommu) {
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iommu_set_exclusion_range(iommu);
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iommu_init_msi(iommu);
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iommu_enable_event_logging(iommu);
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