mirror of
https://github.com/FEX-Emu/linux.git
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Merge remote-tracking branches 'asoc/topic/nau8825' and 'asoc/topic/pxa' into asoc-next
This commit is contained in:
Mark Brown
commit
3db5de560c
102
Documentation/devicetree/bindings/sound/nau8825.txt
Normal file
102
Documentation/devicetree/bindings/sound/nau8825.txt
Normal file
@ -0,0 +1,102 @@
|
||||
Nuvoton NAU8825 audio codec
|
||||
|
||||
This device supports I2C only.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "nuvoton,nau8825"
|
||||
|
||||
- reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1).
|
||||
|
||||
Optional properties:
|
||||
- nuvoton,jkdet-enable: Enable jack detection via JKDET pin.
|
||||
- nuvoton,jkdet-pull-enable: Enable JKDET pin pull. If set - pin pull enabled,
|
||||
otherwise pin in high impedance state.
|
||||
- nuvoton,jkdet-pull-up: Pull-up JKDET pin. If set then JKDET pin is pull up, otherwise pull down.
|
||||
- nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low.
|
||||
|
||||
- nuvoton,vref-impedance: VREF Impedance selection
|
||||
0 - Open
|
||||
1 - 25 kOhm
|
||||
2 - 125 kOhm
|
||||
3 - 2.5 kOhm
|
||||
|
||||
- nuvoton,micbias-voltage: Micbias voltage level.
|
||||
0 - VDDA
|
||||
1 - VDDA
|
||||
2 - VDDA * 1.1
|
||||
3 - VDDA * 1.2
|
||||
4 - VDDA * 1.3
|
||||
5 - VDDA * 1.4
|
||||
6 - VDDA * 1.53
|
||||
7 - VDDA * 1.53
|
||||
|
||||
- nuvoton,sar-threshold-num: Number of buttons supported
|
||||
- nuvoton,sar-threshold: Impedance threshold for each button. Array that contains up to 8 buttons configuration. SAR value is calculated as
|
||||
SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R)
|
||||
where MICBIAS is configured by 'nuvoton,micbias-voltage', SAR_VOLTAGE is configured by 'nuvoton,sar-voltage', R - button impedance.
|
||||
Refer datasheet section 10.2 for more information about threshold calculation.
|
||||
|
||||
- nuvoton,sar-hysteresis: Button impedance measurement hysteresis.
|
||||
|
||||
- nuvoton,sar-voltage: Reference voltage for button impedance measurement.
|
||||
0 - VDDA
|
||||
1 - VDDA
|
||||
2 - VDDA * 1.1
|
||||
3 - VDDA * 1.2
|
||||
4 - VDDA * 1.3
|
||||
5 - VDDA * 1.4
|
||||
6 - VDDA * 1.53
|
||||
7 - VDDA * 1.53
|
||||
|
||||
- nuvoton,sar-compare-time: SAR compare time
|
||||
0 - 500 ns
|
||||
1 - 1 us
|
||||
2 - 2 us
|
||||
3 - 4 us
|
||||
|
||||
- nuvoton,sar-sampling-time: SAR sampling time
|
||||
0 - 2 us
|
||||
1 - 4 us
|
||||
2 - 8 us
|
||||
3 - 16 us
|
||||
|
||||
- nuvoton,short-key-debounce: Button short key press debounce time.
|
||||
0 - 30 ms
|
||||
1 - 50 ms
|
||||
2 - 100 ms
|
||||
3 - 30 ms
|
||||
|
||||
- nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
|
||||
- nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
|
||||
|
||||
- clocks: list of phandle and clock specifier pairs according to common clock bindings for the
|
||||
clocks described in clock-names
|
||||
- clock-names: should include "mclk" for the MCLK master clock
|
||||
|
||||
Example:
|
||||
|
||||
headset: nau8825@1a {
|
||||
compatible = "nuvoton,nau8825";
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
|
||||
nuvoton,jkdet-enable;
|
||||
nuvoton,jkdet-pull-enable;
|
||||
nuvoton,jkdet-pull-up;
|
||||
nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
|
||||
nuvoton,vref-impedance = <2>;
|
||||
nuvoton,micbias-voltage = <6>;
|
||||
// Setup 4 buttons impedance according to Android specification
|
||||
nuvoton,sar-threshold-num = <4>;
|
||||
nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
|
||||
nuvoton,sar-hysteresis = <1>;
|
||||
nuvoton,sar-voltage = <0>;
|
||||
nuvoton,sar-compare-time = <0>;
|
||||
nuvoton,sar-sampling-time = <0>;
|
||||
nuvoton,short-key-debounce = <2>;
|
||||
nuvoton,jack-insert-debounce = <7>;
|
||||
nuvoton,jack-eject-debounce = <7>;
|
||||
|
||||
clock-names = "mclk";
|
||||
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
|
||||
};
|
||||
@ -12,7 +12,6 @@ extern int __pxa2xx_pcm_hw_free(struct snd_pcm_substream *substream);
|
||||
extern int pxa2xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
|
||||
extern snd_pcm_uframes_t pxa2xx_pcm_pointer(struct snd_pcm_substream *substream);
|
||||
extern int __pxa2xx_pcm_prepare(struct snd_pcm_substream *substream);
|
||||
extern void pxa2xx_pcm_dma_irq(int dma_ch, void *dev_id);
|
||||
extern int __pxa2xx_pcm_open(struct snd_pcm_substream *substream);
|
||||
extern int __pxa2xx_pcm_close(struct snd_pcm_substream *substream);
|
||||
extern int pxa2xx_pcm_mmap(struct snd_pcm_substream *substream,
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma/pxa-dma.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
@ -43,7 +44,11 @@ static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
|
||||
.reset = pxa2xx_ac97_reset,
|
||||
};
|
||||
|
||||
static unsigned long pxa2xx_ac97_pcm_out_req = 12;
|
||||
static struct pxad_param pxa2xx_ac97_pcm_out_req = {
|
||||
.prio = PXAD_PRIO_LOWEST,
|
||||
.drcmr = 12,
|
||||
};
|
||||
|
||||
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_out = {
|
||||
.addr = __PREG(PCDR),
|
||||
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
|
||||
@ -51,7 +56,11 @@ static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_out = {
|
||||
.filter_data = &pxa2xx_ac97_pcm_out_req,
|
||||
};
|
||||
|
||||
static unsigned long pxa2xx_ac97_pcm_in_req = 11;
|
||||
static struct pxad_param pxa2xx_ac97_pcm_in_req = {
|
||||
.prio = PXAD_PRIO_LOWEST,
|
||||
.drcmr = 11,
|
||||
};
|
||||
|
||||
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_in = {
|
||||
.addr = __PREG(PCDR),
|
||||
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma/pxa-dma.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
@ -15,8 +16,6 @@
|
||||
#include <sound/pxa2xx-lib.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include "pxa2xx-pcm.h"
|
||||
|
||||
static const struct snd_pcm_hardware pxa2xx_pcm_hardware = {
|
||||
@ -31,7 +30,7 @@ static const struct snd_pcm_hardware pxa2xx_pcm_hardware = {
|
||||
.period_bytes_min = 32,
|
||||
.period_bytes_max = 8192 - 32,
|
||||
.periods_min = 1,
|
||||
.periods_max = PAGE_SIZE/sizeof(pxa_dma_desc),
|
||||
.periods_max = 256,
|
||||
.buffer_bytes_max = 128 * 1024,
|
||||
.fifo_size = 32,
|
||||
};
|
||||
@ -39,65 +38,29 @@ static const struct snd_pcm_hardware pxa2xx_pcm_hardware = {
|
||||
int __pxa2xx_pcm_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct pxa2xx_runtime_data *rtd = runtime->private_data;
|
||||
size_t totsize = params_buffer_bytes(params);
|
||||
size_t period = params_period_bytes(params);
|
||||
pxa_dma_desc *dma_desc;
|
||||
dma_addr_t dma_buff_phys, next_desc_phys;
|
||||
u32 dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
|
||||
struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_dmaengine_dai_dma_data *dma_params;
|
||||
struct dma_slave_config config;
|
||||
int ret;
|
||||
|
||||
/* temporary transition hack */
|
||||
switch (rtd->params->addr_width) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
dcmd |= DCMD_WIDTH1;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
dcmd |= DCMD_WIDTH2;
|
||||
break;
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
dcmd |= DCMD_WIDTH4;
|
||||
break;
|
||||
default:
|
||||
/* can't happen */
|
||||
break;
|
||||
}
|
||||
dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
|
||||
if (!dma_params)
|
||||
return 0;
|
||||
|
||||
switch (rtd->params->maxburst) {
|
||||
case 8:
|
||||
dcmd |= DCMD_BURST8;
|
||||
break;
|
||||
case 16:
|
||||
dcmd |= DCMD_BURST16;
|
||||
break;
|
||||
case 32:
|
||||
dcmd |= DCMD_BURST32;
|
||||
break;
|
||||
}
|
||||
ret = snd_hwparams_to_dma_slave_config(substream, params, &config);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
snd_dmaengine_pcm_set_config_from_dai_data(substream,
|
||||
snd_soc_dai_get_dma_data(rtd->cpu_dai, substream),
|
||||
&config);
|
||||
|
||||
ret = dmaengine_slave_config(chan, &config);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
|
||||
runtime->dma_bytes = totsize;
|
||||
|
||||
dma_desc = rtd->dma_desc_array;
|
||||
next_desc_phys = rtd->dma_desc_array_phys;
|
||||
dma_buff_phys = runtime->dma_addr;
|
||||
do {
|
||||
next_desc_phys += sizeof(pxa_dma_desc);
|
||||
dma_desc->ddadr = next_desc_phys;
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
dma_desc->dsadr = dma_buff_phys;
|
||||
dma_desc->dtadr = rtd->params->addr;
|
||||
} else {
|
||||
dma_desc->dsadr = rtd->params->addr;
|
||||
dma_desc->dtadr = dma_buff_phys;
|
||||
}
|
||||
if (period > totsize)
|
||||
period = totsize;
|
||||
dma_desc->dcmd = dcmd | period | DCMD_ENDIRQEN;
|
||||
dma_desc++;
|
||||
dma_buff_phys += period;
|
||||
} while (totsize -= period);
|
||||
dma_desc[-1].ddadr = rtd->dma_desc_array_phys;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -105,13 +68,6 @@ EXPORT_SYMBOL(__pxa2xx_pcm_hw_params);
|
||||
|
||||
int __pxa2xx_pcm_hw_free(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct pxa2xx_runtime_data *rtd = substream->runtime->private_data;
|
||||
|
||||
if (rtd && rtd->params && rtd->params->filter_data) {
|
||||
unsigned long req = *(unsigned long *) rtd->params->filter_data;
|
||||
DRCMR(req) = 0;
|
||||
}
|
||||
|
||||
snd_pcm_set_runtime_buffer(substream, NULL);
|
||||
return 0;
|
||||
}
|
||||
@ -119,100 +75,36 @@ EXPORT_SYMBOL(__pxa2xx_pcm_hw_free);
|
||||
|
||||
int pxa2xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
||||
{
|
||||
struct pxa2xx_runtime_data *prtd = substream->runtime->private_data;
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
DDADR(prtd->dma_ch) = prtd->dma_desc_array_phys;
|
||||
DCSR(prtd->dma_ch) = DCSR_RUN;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
DCSR(prtd->dma_ch) &= ~DCSR_RUN;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
DCSR(prtd->dma_ch) |= DCSR_RUN;
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
DDADR(prtd->dma_ch) = prtd->dma_desc_array_phys;
|
||||
DCSR(prtd->dma_ch) |= DCSR_RUN;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
return snd_dmaengine_pcm_trigger(substream, cmd);
|
||||
}
|
||||
EXPORT_SYMBOL(pxa2xx_pcm_trigger);
|
||||
|
||||
snd_pcm_uframes_t
|
||||
pxa2xx_pcm_pointer(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct pxa2xx_runtime_data *prtd = runtime->private_data;
|
||||
|
||||
dma_addr_t ptr = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
|
||||
DSADR(prtd->dma_ch) : DTADR(prtd->dma_ch);
|
||||
snd_pcm_uframes_t x = bytes_to_frames(runtime, ptr - runtime->dma_addr);
|
||||
|
||||
if (x == runtime->buffer_size)
|
||||
x = 0;
|
||||
return x;
|
||||
return snd_dmaengine_pcm_pointer(substream);
|
||||
}
|
||||
EXPORT_SYMBOL(pxa2xx_pcm_pointer);
|
||||
|
||||
int __pxa2xx_pcm_prepare(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct pxa2xx_runtime_data *prtd = substream->runtime->private_data;
|
||||
unsigned long req;
|
||||
|
||||
if (!prtd || !prtd->params)
|
||||
return 0;
|
||||
|
||||
if (prtd->dma_ch == -1)
|
||||
return -EINVAL;
|
||||
|
||||
DCSR(prtd->dma_ch) &= ~DCSR_RUN;
|
||||
DCSR(prtd->dma_ch) = 0;
|
||||
DCMD(prtd->dma_ch) = 0;
|
||||
req = *(unsigned long *) prtd->params->filter_data;
|
||||
DRCMR(req) = prtd->dma_ch | DRCMR_MAPVLD;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(__pxa2xx_pcm_prepare);
|
||||
|
||||
void pxa2xx_pcm_dma_irq(int dma_ch, void *dev_id)
|
||||
{
|
||||
struct snd_pcm_substream *substream = dev_id;
|
||||
int dcsr;
|
||||
|
||||
dcsr = DCSR(dma_ch);
|
||||
DCSR(dma_ch) = dcsr & ~DCSR_STOPIRQEN;
|
||||
|
||||
if (dcsr & DCSR_ENDINTR) {
|
||||
snd_pcm_period_elapsed(substream);
|
||||
} else {
|
||||
printk(KERN_ERR "DMA error on channel %d (DCSR=%#x)\n",
|
||||
dma_ch, dcsr);
|
||||
snd_pcm_stop_xrun(substream);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(pxa2xx_pcm_dma_irq);
|
||||
|
||||
int __pxa2xx_pcm_open(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct pxa2xx_runtime_data *rtd;
|
||||
struct snd_dmaengine_dai_dma_data *dma_params;
|
||||
int ret;
|
||||
|
||||
runtime->hw = pxa2xx_pcm_hardware;
|
||||
|
||||
dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
|
||||
if (!dma_params)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* For mysterious reasons (and despite what the manual says)
|
||||
* playback samples are lost if the DMA count is not a multiple
|
||||
@ -221,48 +113,27 @@ int __pxa2xx_pcm_open(struct snd_pcm_substream *substream)
|
||||
ret = snd_pcm_hw_constraint_step(runtime, 0,
|
||||
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
|
||||
if (ret)
|
||||
goto out;
|
||||
return ret;
|
||||
|
||||
ret = snd_pcm_hw_constraint_step(runtime, 0,
|
||||
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
|
||||
if (ret)
|
||||
goto out;
|
||||
return ret;
|
||||
|
||||
ret = snd_pcm_hw_constraint_integer(runtime,
|
||||
SNDRV_PCM_HW_PARAM_PERIODS);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
return ret;
|
||||
|
||||
ret = -ENOMEM;
|
||||
rtd = kzalloc(sizeof(*rtd), GFP_KERNEL);
|
||||
if (!rtd)
|
||||
goto out;
|
||||
rtd->dma_desc_array =
|
||||
dma_alloc_writecombine(substream->pcm->card->dev, PAGE_SIZE,
|
||||
&rtd->dma_desc_array_phys, GFP_KERNEL);
|
||||
if (!rtd->dma_desc_array)
|
||||
goto err1;
|
||||
|
||||
rtd->dma_ch = -1;
|
||||
runtime->private_data = rtd;
|
||||
return 0;
|
||||
|
||||
err1:
|
||||
kfree(rtd);
|
||||
out:
|
||||
return ret;
|
||||
return snd_dmaengine_pcm_open_request_chan(substream,
|
||||
pxad_filter_fn,
|
||||
dma_params->filter_data);
|
||||
}
|
||||
EXPORT_SYMBOL(__pxa2xx_pcm_open);
|
||||
|
||||
int __pxa2xx_pcm_close(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct pxa2xx_runtime_data *rtd = runtime->private_data;
|
||||
|
||||
dma_free_writecombine(substream->pcm->card->dev, PAGE_SIZE,
|
||||
rtd->dma_desc_array, rtd->dma_desc_array_phys);
|
||||
kfree(rtd);
|
||||
return 0;
|
||||
return snd_dmaengine_pcm_close_release_chan(substream);
|
||||
}
|
||||
EXPORT_SYMBOL(__pxa2xx_pcm_close);
|
||||
|
||||
|
||||
@ -46,17 +46,13 @@ static int pxa2xx_pcm_open(struct snd_pcm_substream *substream)
|
||||
|
||||
rtd->params = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
|
||||
client->playback_params : client->capture_params;
|
||||
ret = pxa_request_dma("dma", DMA_PRIO_LOW,
|
||||
pxa2xx_pcm_dma_irq, substream);
|
||||
if (ret < 0)
|
||||
goto err2;
|
||||
rtd->dma_ch = ret;
|
||||
|
||||
ret = client->startup(substream);
|
||||
if (!ret)
|
||||
goto out;
|
||||
goto err2;
|
||||
|
||||
return 0;
|
||||
|
||||
pxa_free_dma(rtd->dma_ch);
|
||||
err2:
|
||||
__pxa2xx_pcm_close(substream);
|
||||
out:
|
||||
@ -66,9 +62,7 @@ static int pxa2xx_pcm_open(struct snd_pcm_substream *substream)
|
||||
static int pxa2xx_pcm_close(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct pxa2xx_pcm_client *client = substream->private_data;
|
||||
struct pxa2xx_runtime_data *rtd = substream->runtime->private_data;
|
||||
|
||||
pxa_free_dma(rtd->dma_ch);
|
||||
client->shutdown(substream);
|
||||
|
||||
return __pxa2xx_pcm_close(substream);
|
||||
|
||||
@ -13,8 +13,6 @@
|
||||
struct pxa2xx_runtime_data {
|
||||
int dma_ch;
|
||||
struct snd_dmaengine_dai_dma_data *params;
|
||||
struct pxa_dma_desc *dma_desc_array;
|
||||
dma_addr_t dma_desc_array_phys;
|
||||
};
|
||||
|
||||
struct pxa2xx_pcm_client {
|
||||
|
||||
@ -81,6 +81,7 @@ config SND_SOC_ALL_CODECS
|
||||
select SND_SOC_MAX9877 if I2C
|
||||
select SND_SOC_MC13783 if MFD_MC13XXX
|
||||
select SND_SOC_ML26124 if I2C
|
||||
select SND_SOC_NAU8825 if I2C
|
||||
select SND_SOC_PCM1681 if I2C
|
||||
select SND_SOC_PCM1792A if SPI_MASTER
|
||||
select SND_SOC_PCM3008
|
||||
@ -907,6 +908,9 @@ config SND_SOC_MC13783
|
||||
config SND_SOC_ML26124
|
||||
tristate
|
||||
|
||||
config SND_SOC_NAU8825
|
||||
tristate
|
||||
|
||||
config SND_SOC_TPA6130A2
|
||||
tristate "Texas Instruments TPA6130A2 headphone amplifier"
|
||||
depends on I2C
|
||||
|
||||
@ -74,6 +74,7 @@ snd-soc-max98925-objs := max98925.o
|
||||
snd-soc-max9850-objs := max9850.o
|
||||
snd-soc-mc13783-objs := mc13783.o
|
||||
snd-soc-ml26124-objs := ml26124.o
|
||||
snd-soc-nau8825-objs := nau8825.o
|
||||
snd-soc-pcm1681-objs := pcm1681.o
|
||||
snd-soc-pcm1792a-codec-objs := pcm1792a.o
|
||||
snd-soc-pcm3008-objs := pcm3008.o
|
||||
@ -268,6 +269,7 @@ obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
|
||||
obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
|
||||
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
|
||||
obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
|
||||
obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o
|
||||
obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o
|
||||
obj-$(CONFIG_SND_SOC_PCM1792A) += snd-soc-pcm1792a-codec.o
|
||||
obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
|
||||
|
||||
1309
sound/soc/codecs/nau8825.c
Normal file
1309
sound/soc/codecs/nau8825.c
Normal file
File diff suppressed because it is too large
Load Diff
341
sound/soc/codecs/nau8825.h
Normal file
341
sound/soc/codecs/nau8825.h
Normal file
@ -0,0 +1,341 @@
|
||||
/*
|
||||
* NAU8825 ALSA SoC audio driver
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
* Author: Anatol Pomozov <anatol.pomozov@chrominium.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __NAU8825_H__
|
||||
#define __NAU8825_H__
|
||||
|
||||
#define NAU8825_REG_RESET 0x00
|
||||
#define NAU8825_REG_ENA_CTRL 0x01
|
||||
#define NAU8825_REG_CLK_DIVIDER 0x03
|
||||
#define NAU8825_REG_FLL1 0x04
|
||||
#define NAU8825_REG_FLL2 0x05
|
||||
#define NAU8825_REG_FLL3 0x06
|
||||
#define NAU8825_REG_FLL4 0x07
|
||||
#define NAU8825_REG_FLL5 0x08
|
||||
#define NAU8825_REG_FLL6 0x09
|
||||
#define NAU8825_REG_FLL_VCO_RSV 0x0a
|
||||
#define NAU8825_REG_HSD_CTRL 0x0c
|
||||
#define NAU8825_REG_JACK_DET_CTRL 0x0d
|
||||
#define NAU8825_REG_INTERRUPT_MASK 0x0f
|
||||
#define NAU8825_REG_IRQ_STATUS 0x10
|
||||
#define NAU8825_REG_INT_CLR_KEY_STATUS 0x11
|
||||
#define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12
|
||||
#define NAU8825_REG_SAR_CTRL 0x13
|
||||
#define NAU8825_REG_KEYDET_CTRL 0x14
|
||||
#define NAU8825_REG_VDET_THRESHOLD_1 0x15
|
||||
#define NAU8825_REG_VDET_THRESHOLD_2 0x16
|
||||
#define NAU8825_REG_VDET_THRESHOLD_3 0x17
|
||||
#define NAU8825_REG_VDET_THRESHOLD_4 0x18
|
||||
#define NAU8825_REG_GPIO34_CTRL 0x19
|
||||
#define NAU8825_REG_GPIO12_CTRL 0x1a
|
||||
#define NAU8825_REG_TDM_CTRL 0x1b
|
||||
#define NAU8825_REG_I2S_PCM_CTRL1 0x1c
|
||||
#define NAU8825_REG_I2S_PCM_CTRL2 0x1d
|
||||
#define NAU8825_REG_LEFT_TIME_SLOT 0x1e
|
||||
#define NAU8825_REG_RIGHT_TIME_SLOT 0x1f
|
||||
#define NAU8825_REG_BIQ_CTRL 0x20
|
||||
#define NAU8825_REG_BIQ_COF1 0x21
|
||||
#define NAU8825_REG_BIQ_COF2 0x22
|
||||
#define NAU8825_REG_BIQ_COF3 0x23
|
||||
#define NAU8825_REG_BIQ_COF4 0x24
|
||||
#define NAU8825_REG_BIQ_COF5 0x25
|
||||
#define NAU8825_REG_BIQ_COF6 0x26
|
||||
#define NAU8825_REG_BIQ_COF7 0x27
|
||||
#define NAU8825_REG_BIQ_COF8 0x28
|
||||
#define NAU8825_REG_BIQ_COF9 0x29
|
||||
#define NAU8825_REG_BIQ_COF10 0x2a
|
||||
#define NAU8825_REG_ADC_RATE 0x2b
|
||||
#define NAU8825_REG_DAC_CTRL1 0x2c
|
||||
#define NAU8825_REG_DAC_CTRL2 0x2d
|
||||
#define NAU8825_REG_DAC_DGAIN_CTRL 0x2f
|
||||
#define NAU8825_REG_ADC_DGAIN_CTRL 0x30
|
||||
#define NAU8825_REG_MUTE_CTRL 0x31
|
||||
#define NAU8825_REG_HSVOL_CTRL 0x32
|
||||
#define NAU8825_REG_DACL_CTRL 0x33
|
||||
#define NAU8825_REG_DACR_CTRL 0x34
|
||||
#define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38
|
||||
#define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39
|
||||
#define NAU8825_REG_ADC_DRC_SLOPES 0x3a
|
||||
#define NAU8825_REG_ADC_DRC_ATKDCY 0x3b
|
||||
#define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45
|
||||
#define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46
|
||||
#define NAU8825_REG_DAC_DRC_SLOPES 0x47
|
||||
#define NAU8825_REG_DAC_DRC_ATKDCY 0x48
|
||||
#define NAU8825_REG_IMM_MODE_CTRL 0x4c
|
||||
#define NAU8825_REG_IMM_RMS_L 0x4d
|
||||
#define NAU8825_REG_IMM_RMS_R 0x4e
|
||||
#define NAU8825_REG_CLASSG_CTRL 0x50
|
||||
#define NAU8825_REG_OPT_EFUSE_CTRL 0x51
|
||||
#define NAU8825_REG_MISC_CTRL 0x55
|
||||
#define NAU8825_REG_I2C_DEVICE_ID 0x58
|
||||
#define NAU8825_REG_SARDOUT_RAM_STATUS 0x59
|
||||
#define NAU8825_REG_BIAS_ADJ 0x66
|
||||
#define NAU8825_REG_TRIM_SETTINGS 0x68
|
||||
#define NAU8825_REG_ANALOG_CONTROL_1 0x69
|
||||
#define NAU8825_REG_ANALOG_CONTROL_2 0x6a
|
||||
#define NAU8825_REG_ANALOG_ADC_1 0x71
|
||||
#define NAU8825_REG_ANALOG_ADC_2 0x72
|
||||
#define NAU8825_REG_RDAC 0x73
|
||||
#define NAU8825_REG_MIC_BIAS 0x74
|
||||
#define NAU8825_REG_BOOST 0x76
|
||||
#define NAU8825_REG_FEPGA 0x77
|
||||
#define NAU8825_REG_POWER_UP_CONTROL 0x7f
|
||||
#define NAU8825_REG_CHARGE_PUMP 0x80
|
||||
#define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81
|
||||
#define NAU8825_REG_GENERAL_STATUS 0x82
|
||||
#define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS
|
||||
|
||||
/* ENA_CTRL (0x1) */
|
||||
#define NAU8825_ENABLE_DACR_SFT 10
|
||||
#define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT)
|
||||
#define NAU8825_ENABLE_DACL_SFT 9
|
||||
#define NAU8825_ENABLE_ADC_SFT 8
|
||||
#define NAU8825_ENABLE_SAR_SFT 1
|
||||
|
||||
/* CLK_DIVIDER (0x3) */
|
||||
#define NAU8825_CLK_SRC_SFT 15
|
||||
#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT)
|
||||
#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT)
|
||||
#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT)
|
||||
#define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0)
|
||||
|
||||
/* FLL1 (0x04) */
|
||||
#define NAU8825_FLL_RATIO_MASK (0x7f << 0)
|
||||
|
||||
/* FLL3 (0x06) */
|
||||
#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
|
||||
|
||||
/* FLL4 (0x07) */
|
||||
#define NAU8825_FLL_REF_DIV_MASK (0x3 << 10)
|
||||
|
||||
/* FLL5 (0x08) */
|
||||
#define NAU8825_FLL_FILTER_SW_MASK (0x1 << 14)
|
||||
|
||||
/* FLL6 (0x9) */
|
||||
#define NAU8825_DCO_EN_MASK (0x1 << 15)
|
||||
#define NAU8825_DCO_EN (0x1 << 15)
|
||||
#define NAU8825_DCO_DIS (0x0 << 15)
|
||||
#define NAU8825_SDM_EN_MASK (0x1 << 14)
|
||||
#define NAU8825_SDM_EN (0x1 << 14)
|
||||
#define NAU8825_SDM_DIS (0x0 << 14)
|
||||
|
||||
/* HSD_CTRL (0xc) */
|
||||
#define NAU8825_HSD_AUTO_MODE (1 << 6)
|
||||
/* 0 - short to GND, 1 - open */
|
||||
#define NAU8825_SPKR_DWN1R (1 << 1)
|
||||
#define NAU8825_SPKR_DWN1L (1 << 0)
|
||||
|
||||
/* JACK_DET_CTRL (0xd) */
|
||||
#define NAU8825_JACK_DET_RESTART (1 << 9)
|
||||
#define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5
|
||||
#define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT)
|
||||
#define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2
|
||||
#define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT)
|
||||
#define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */
|
||||
|
||||
/* INTERRUPT_MASK (0xf) */
|
||||
#define NAU8825_IRQ_OUTPUT_EN (1 << 11)
|
||||
#define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10)
|
||||
#define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7)
|
||||
#define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5)
|
||||
#define NAU8825_IRQ_EJECT_EN (1 << 2)
|
||||
|
||||
/* IRQ_STATUS (0x10) */
|
||||
#define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10)
|
||||
#define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9)
|
||||
#define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8)
|
||||
#define NAU8825_KEY_IRQ_MASK (0x7 << 5)
|
||||
#define NAU8825_KEY_RELEASE_IRQ (1 << 7)
|
||||
#define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6)
|
||||
#define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5)
|
||||
#define NAU8825_MIC_DETECTION_IRQ (1 << 4)
|
||||
#define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2)
|
||||
#define NAU8825_JACK_EJECTION_DETECTED (1 << 2)
|
||||
#define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0)
|
||||
#define NAU8825_JACK_INSERTION_DETECTED (1 << 0)
|
||||
|
||||
/* INTERRUPT_DIS_CTRL (0x12) */
|
||||
#define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10)
|
||||
#define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7)
|
||||
#define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5)
|
||||
#define NAU8825_IRQ_EJECT_DIS (1 << 2)
|
||||
|
||||
/* SAR_CTRL (0x13) */
|
||||
#define NAU8825_SAR_ADC_EN_SFT 12
|
||||
#define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT)
|
||||
#define NAU8825_SAR_INPUT_MASK (1 << 11)
|
||||
#define NAU8825_SAR_INPUT_JKSLV (1 << 11)
|
||||
#define NAU8825_SAR_INPUT_JKR2 (0 << 11)
|
||||
#define NAU8825_SAR_TRACKING_GAIN_SFT 8
|
||||
#define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT)
|
||||
#define NAU8825_SAR_COMPARE_TIME_SFT 2
|
||||
#define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2)
|
||||
#define NAU8825_SAR_SAMPLING_TIME_SFT 0
|
||||
#define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0)
|
||||
|
||||
/* KEYDET_CTRL (0x14) */
|
||||
#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12
|
||||
#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT)
|
||||
#define NAU8825_KEYDET_LEVELS_NR_SFT 8
|
||||
#define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8)
|
||||
#define NAU8825_KEYDET_HYSTERESIS_SFT 0
|
||||
#define NAU8825_KEYDET_HYSTERESIS_MASK 0xf
|
||||
|
||||
/* GPIO12_CTRL (0x1a) */
|
||||
#define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */
|
||||
#define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */
|
||||
#define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */
|
||||
|
||||
/* I2S_PCM_CTRL1 (0x1c) */
|
||||
#define NAU8825_I2S_BP_SFT 7
|
||||
#define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT)
|
||||
#define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT)
|
||||
#define NAU8825_I2S_PCMB_SFT 6
|
||||
#define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT)
|
||||
#define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT)
|
||||
#define NAU8825_I2S_DL_SFT 2
|
||||
#define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT)
|
||||
#define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT)
|
||||
#define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT)
|
||||
#define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT)
|
||||
#define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT)
|
||||
#define NAU8825_I2S_DF_SFT 0
|
||||
#define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT)
|
||||
#define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT)
|
||||
#define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT)
|
||||
#define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT)
|
||||
#define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT)
|
||||
|
||||
/* I2S_PCM_CTRL2 (0x1d) */
|
||||
#define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
|
||||
#define NAU8825_I2S_MS_SFT 3
|
||||
#define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT)
|
||||
#define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT)
|
||||
#define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT)
|
||||
|
||||
/* ADC_RATE (0x2b) */
|
||||
#define NAU8825_ADC_SYNC_DOWN_SFT 0
|
||||
#define NAU8825_ADC_SYNC_DOWN_MASK 0x3
|
||||
#define NAU8825_ADC_SYNC_DOWN_32 0
|
||||
#define NAU8825_ADC_SYNC_DOWN_64 1
|
||||
#define NAU8825_ADC_SYNC_DOWN_128 2
|
||||
#define NAU8825_ADC_SYNC_DOWN_256 3
|
||||
|
||||
/* DAC_CTRL1 (0x2c) */
|
||||
#define NAU8825_DAC_CLIP_OFF (1 << 7)
|
||||
#define NAU8825_DAC_OVERSAMPLE_SFT 0
|
||||
#define NAU8825_DAC_OVERSAMPLE_MASK 0x7
|
||||
#define NAU8825_DAC_OVERSAMPLE_64 0
|
||||
#define NAU8825_DAC_OVERSAMPLE_256 1
|
||||
#define NAU8825_DAC_OVERSAMPLE_128 2
|
||||
#define NAU8825_DAC_OVERSAMPLE_32 4
|
||||
|
||||
/* MUTE_CTRL (0x31) */
|
||||
#define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9)
|
||||
#define NAU8825_DAC_SOFT_MUTE (1 << 9)
|
||||
|
||||
/* HSVOL_CTRL (0x32) */
|
||||
#define NAU8825_HP_MUTE (1 << 15)
|
||||
|
||||
/* DACL_CTRL (0x33) */
|
||||
#define NAU8825_DACL_CH_SEL_SFT 9
|
||||
|
||||
/* DACR_CTRL (0x34) */
|
||||
#define NAU8825_DACR_CH_SEL_SFT 9
|
||||
|
||||
/* I2C_DEVICE_ID (0x58) */
|
||||
#define NAU8825_GPIO2JD1 (1 << 7)
|
||||
#define NAU8825_SOFTWARE_ID_MASK 0x3
|
||||
#define NAU8825_SOFTWARE_ID_NAU8825 0x0
|
||||
|
||||
/* BIAS_ADJ (0x66) */
|
||||
#define NAU8825_BIAS_VMID (1 << 6)
|
||||
#define NAU8825_BIAS_VMID_SEL_SFT 4
|
||||
#define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT)
|
||||
|
||||
/* ANALOG_CONTROL_2 (0x6a) */
|
||||
#define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12)
|
||||
#define NAU8825_DAC_CAPACITOR_MSB (1 << 1)
|
||||
#define NAU8825_DAC_CAPACITOR_LSB (1 << 0)
|
||||
|
||||
/* ANALOG_ADC_2 (0x72) */
|
||||
#define NAU8825_ADC_VREFSEL_MASK (0x3 << 8)
|
||||
#define NAU8825_ADC_VREFSEL_ANALOG (0 << 8)
|
||||
#define NAU8825_ADC_VREFSEL_VMID (1 << 8)
|
||||
#define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8)
|
||||
#define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8)
|
||||
#define NAU8825_POWERUP_ADCL (1 << 6)
|
||||
|
||||
/* MIC_BIAS (0x74) */
|
||||
#define NAU8825_MICBIAS_JKSLV (1 << 14)
|
||||
#define NAU8825_MICBIAS_JKR2 (1 << 12)
|
||||
#define NAU8825_MICBIAS_POWERUP_SFT 8
|
||||
#define NAU8825_MICBIAS_VOLTAGE_SFT 0
|
||||
#define NAU8825_MICBIAS_VOLTAGE_MASK 0x7
|
||||
|
||||
/* BOOST (0x76) */
|
||||
#define NAU8825_PRECHARGE_DIS (1 << 13)
|
||||
#define NAU8825_GLOBAL_BIAS_EN (1 << 12)
|
||||
#define NAU8825_HP_BOOST_G_DIS (1 << 8)
|
||||
#define NAU8825_SHORT_SHUTDOWN_EN (1 << 6)
|
||||
|
||||
/* POWER_UP_CONTROL (0x7f) */
|
||||
#define NAU8825_POWERUP_INTEGR_R (1 << 5)
|
||||
#define NAU8825_POWERUP_INTEGR_L (1 << 4)
|
||||
#define NAU8825_POWERUP_DRV_IN_R (1 << 3)
|
||||
#define NAU8825_POWERUP_DRV_IN_L (1 << 2)
|
||||
#define NAU8825_POWERUP_HP_DRV_R (1 << 1)
|
||||
#define NAU8825_POWERUP_HP_DRV_L (1 << 0)
|
||||
|
||||
/* CHARGE_PUMP (0x80) */
|
||||
#define NAU8825_JAMNODCLOW (1 << 10)
|
||||
#define NAU8825_POWER_DOWN_DACR (1 << 9)
|
||||
#define NAU8825_POWER_DOWN_DACL (1 << 8)
|
||||
#define NAU8825_CHANRGE_PUMP_EN (1 << 5)
|
||||
|
||||
|
||||
/* System Clock Source */
|
||||
enum {
|
||||
NAU8825_CLK_MCLK = 0,
|
||||
NAU8825_CLK_INTERNAL,
|
||||
};
|
||||
|
||||
struct nau8825 {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
struct snd_soc_dapm_context *dapm;
|
||||
struct snd_soc_jack *jack;
|
||||
struct clk *mclk;
|
||||
int irq;
|
||||
int mclk_freq; /* 0 - mclk is disabled */
|
||||
int button_pressed;
|
||||
int micbias_voltage;
|
||||
int vref_impedance;
|
||||
bool jkdet_enable;
|
||||
bool jkdet_pull_enable;
|
||||
bool jkdet_pull_up;
|
||||
int jkdet_polarity;
|
||||
int sar_threshold_num;
|
||||
int sar_threshold[8];
|
||||
int sar_hysteresis;
|
||||
int sar_voltage;
|
||||
int sar_compare_time;
|
||||
int sar_sampling_time;
|
||||
int key_debounce;
|
||||
int jack_insert_debounce;
|
||||
int jack_eject_debounce;
|
||||
};
|
||||
|
||||
int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
|
||||
struct snd_soc_jack *jack);
|
||||
|
||||
|
||||
#endif /* __NAU8825_H__ */
|
||||
@ -15,6 +15,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma/pxa-dma.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/ac97_codec.h>
|
||||
@ -49,7 +50,11 @@ static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
|
||||
.reset = pxa2xx_ac97_cold_reset,
|
||||
};
|
||||
|
||||
static unsigned long pxa2xx_ac97_pcm_stereo_in_req = 11;
|
||||
static struct pxad_param pxa2xx_ac97_pcm_stereo_in_req = {
|
||||
.prio = PXAD_PRIO_LOWEST,
|
||||
.drcmr = 11,
|
||||
};
|
||||
|
||||
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_in = {
|
||||
.addr = __PREG(PCDR),
|
||||
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
|
||||
@ -57,7 +62,11 @@ static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_in = {
|
||||
.filter_data = &pxa2xx_ac97_pcm_stereo_in_req,
|
||||
};
|
||||
|
||||
static unsigned long pxa2xx_ac97_pcm_stereo_out_req = 12;
|
||||
static struct pxad_param pxa2xx_ac97_pcm_stereo_out_req = {
|
||||
.prio = PXAD_PRIO_LOWEST,
|
||||
.drcmr = 12,
|
||||
};
|
||||
|
||||
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_out = {
|
||||
.addr = __PREG(PCDR),
|
||||
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
|
||||
@ -65,7 +74,10 @@ static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_out = {
|
||||
.filter_data = &pxa2xx_ac97_pcm_stereo_out_req,
|
||||
};
|
||||
|
||||
static unsigned long pxa2xx_ac97_pcm_aux_mono_out_req = 10;
|
||||
static struct pxad_param pxa2xx_ac97_pcm_aux_mono_out_req = {
|
||||
.prio = PXAD_PRIO_LOWEST,
|
||||
.drcmr = 10,
|
||||
};
|
||||
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_out = {
|
||||
.addr = __PREG(MODR),
|
||||
.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
|
||||
@ -73,7 +85,10 @@ static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_out = {
|
||||
.filter_data = &pxa2xx_ac97_pcm_aux_mono_out_req,
|
||||
};
|
||||
|
||||
static unsigned long pxa2xx_ac97_pcm_aux_mono_in_req = 9;
|
||||
static struct pxad_param pxa2xx_ac97_pcm_aux_mono_in_req = {
|
||||
.prio = PXAD_PRIO_LOWEST,
|
||||
.drcmr = 9,
|
||||
};
|
||||
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_in = {
|
||||
.addr = __PREG(MODR),
|
||||
.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
|
||||
@ -81,7 +96,10 @@ static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_in = {
|
||||
.filter_data = &pxa2xx_ac97_pcm_aux_mono_in_req,
|
||||
};
|
||||
|
||||
static unsigned long pxa2xx_ac97_pcm_aux_mic_mono_req = 8;
|
||||
static struct pxad_param pxa2xx_ac97_pcm_aux_mic_mono_req = {
|
||||
.prio = PXAD_PRIO_LOWEST,
|
||||
.drcmr = 8,
|
||||
};
|
||||
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_mic_mono_in = {
|
||||
.addr = __PREG(MCDR),
|
||||
.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
|
||||
@ -89,9 +107,8 @@ static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_mic_mono_in = {
|
||||
.filter_data = &pxa2xx_ac97_pcm_aux_mic_mono_req,
|
||||
};
|
||||
|
||||
static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *cpu_dai)
|
||||
static int pxa2xx_ac97_hifi_startup(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *cpu_dai)
|
||||
{
|
||||
struct snd_dmaengine_dai_dma_data *dma_data;
|
||||
|
||||
@ -105,9 +122,8 @@ static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *cpu_dai)
|
||||
static int pxa2xx_ac97_aux_startup(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *cpu_dai)
|
||||
{
|
||||
struct snd_dmaengine_dai_dma_data *dma_data;
|
||||
|
||||
@ -121,9 +137,8 @@ static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *cpu_dai)
|
||||
static int pxa2xx_ac97_mic_startup(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *cpu_dai)
|
||||
{
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
return -ENODEV;
|
||||
@ -139,15 +154,15 @@ static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
|
||||
SNDRV_PCM_RATE_48000)
|
||||
|
||||
static const struct snd_soc_dai_ops pxa_ac97_hifi_dai_ops = {
|
||||
.hw_params = pxa2xx_ac97_hw_params,
|
||||
.startup = pxa2xx_ac97_hifi_startup,
|
||||
};
|
||||
|
||||
static const struct snd_soc_dai_ops pxa_ac97_aux_dai_ops = {
|
||||
.hw_params = pxa2xx_ac97_hw_aux_params,
|
||||
.startup = pxa2xx_ac97_aux_startup,
|
||||
};
|
||||
|
||||
static const struct snd_soc_dai_ops pxa_ac97_mic_dai_ops = {
|
||||
.hw_params = pxa2xx_ac97_hw_mic_params,
|
||||
.startup = pxa2xx_ac97_mic_startup,
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
@ -319,6 +319,9 @@ static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
|
||||
/* Along with FIFO servicing */
|
||||
SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);
|
||||
|
||||
snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
|
||||
&pxa2xx_i2s_pcm_stereo_in);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -15,8 +15,6 @@
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/pxa2xx-lib.h>
|
||||
@ -27,11 +25,8 @@
|
||||
static int pxa2xx_pcm_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct pxa2xx_runtime_data *prtd = runtime->private_data;
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_dmaengine_dai_dma_data *dma;
|
||||
int ret;
|
||||
|
||||
dma = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
|
||||
|
||||
@ -40,40 +35,13 @@ static int pxa2xx_pcm_hw_params(struct snd_pcm_substream *substream,
|
||||
if (!dma)
|
||||
return 0;
|
||||
|
||||
/* this may get called several times by oss emulation
|
||||
* with different params */
|
||||
if (prtd->params == NULL) {
|
||||
prtd->params = dma;
|
||||
ret = pxa_request_dma("name", DMA_PRIO_LOW,
|
||||
pxa2xx_pcm_dma_irq, substream);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
prtd->dma_ch = ret;
|
||||
} else if (prtd->params != dma) {
|
||||
pxa_free_dma(prtd->dma_ch);
|
||||
prtd->params = dma;
|
||||
ret = pxa_request_dma("name", DMA_PRIO_LOW,
|
||||
pxa2xx_pcm_dma_irq, substream);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
prtd->dma_ch = ret;
|
||||
}
|
||||
|
||||
return __pxa2xx_pcm_hw_params(substream, params);
|
||||
}
|
||||
|
||||
static int pxa2xx_pcm_hw_free(struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct pxa2xx_runtime_data *prtd = substream->runtime->private_data;
|
||||
|
||||
__pxa2xx_pcm_hw_free(substream);
|
||||
|
||||
if (prtd->dma_ch >= 0) {
|
||||
pxa_free_dma(prtd->dma_ch);
|
||||
prtd->dma_ch = -1;
|
||||
prtd->params = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user