diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index 66388ce16c30..4e0b16500686 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -18,8 +18,7 @@
 #define SH_CACHE_ASSOC		8
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
-#define CCR1		0xffffffec
-#define CCR		CCR1
+#define CCR		0xffffffec
 
 #define CCR_CACHE_CE	0x01	/* Cache enable */
 #define CCR_CACHE_WT	0x06    /* CCR[bit1=1,bit2=1] */
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
index d88774169b58..afe228b3f493 100644
--- a/include/asm-sh/cpu-sh2a/cache.h
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -17,12 +17,9 @@
 #define SH_CACHE_COMBINED	4
 #define SH_CACHE_ASSOC		8
 
-#define CCR1		0xfffc1000
+#define CCR		0xfffc1000 /* CCR1 */
 #define CCR2		0xfffc1004
 
-/* CCR1 behaves more like the traditional CCR */
-#define CCR		CCR1
-
 /*
  * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
  * listed here are reserved.
@@ -41,4 +38,3 @@
 #define CCR_CACHE_INVALIDATE	(CCR_CACHE_OCI | CCR_CACHE_ICI)
 
 #endif /* __ASM_CPU_SH2A_CACHE_H */
-