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qla3xxx: Adding support for the Agere PHY (ET1011C)
This PHY support patch was written by Benjamin Li. Signed-off-by: Benjamin Li <benjamin.li@qlogic.com> Signed-off-by: Ron Mercer <ron.mercer@qlogic.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Ron Mercer
Jeff Garzik
parent
ec8263839a
commit
3efedf2e5b
@ -71,6 +71,30 @@ static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
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MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
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/*
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* These are the known PHY's which are used
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*/
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typedef enum {
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PHY_TYPE_UNKNOWN = 0,
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PHY_VITESSE_VSC8211,
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PHY_AGERE_ET1011C,
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MAX_PHY_DEV_TYPES
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} PHY_DEVICE_et;
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typedef struct {
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PHY_DEVICE_et phyDevice;
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u32 phyIdOUI;
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u16 phyIdModel;
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char *name;
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} PHY_DEVICE_INFO_t;
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const PHY_DEVICE_INFO_t PHY_DEVICES[] =
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{{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
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{PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
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{PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
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};
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/*
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* Caller must take hw_lock.
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*/
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@ -662,7 +686,7 @@ static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
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}
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static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
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u16 regAddr, u16 value, u32 mac_index)
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u16 regAddr, u16 value, u32 phyAddr)
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{
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struct ql3xxx_port_registers __iomem *port_regs =
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qdev->mem_map_registers;
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@ -680,7 +704,7 @@ static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
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}
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ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
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PHYAddr[mac_index] | regAddr);
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phyAddr | regAddr);
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ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
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@ -701,7 +725,7 @@ static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
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}
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static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
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u16 * value, u32 mac_index)
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u16 * value, u32 phyAddr)
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{
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struct ql3xxx_port_registers __iomem *port_regs =
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qdev->mem_map_registers;
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@ -720,7 +744,7 @@ static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
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}
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ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
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PHYAddr[mac_index] | regAddr);
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phyAddr | regAddr);
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ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
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(MAC_MII_CONTROL_RC << 16));
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@ -850,28 +874,31 @@ static void ql_petbi_start_neg(struct ql3_adapter *qdev)
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}
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static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
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static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
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{
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ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
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mac_index);
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PHYAddr[qdev->mac_index]);
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}
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static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
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static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
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{
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u16 reg;
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/* Enable Auto-negotiation sense */
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ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®, mac_index);
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ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
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PHYAddr[qdev->mac_index]);
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reg |= PETBI_TBI_AUTO_SENSE;
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ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
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ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
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PHYAddr[qdev->mac_index]);
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ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
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PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
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PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
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PHYAddr[qdev->mac_index]);
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ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
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PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
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PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
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mac_index);
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PHYAddr[qdev->mac_index]);
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}
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static void ql_petbi_init(struct ql3_adapter *qdev)
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@ -880,10 +907,10 @@ static void ql_petbi_init(struct ql3_adapter *qdev)
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ql_petbi_start_neg(qdev);
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}
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static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
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static void ql_petbi_init_ex(struct ql3_adapter *qdev)
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{
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ql_petbi_reset_ex(qdev, mac_index);
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ql_petbi_start_neg_ex(qdev, mac_index);
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ql_petbi_reset_ex(qdev);
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ql_petbi_start_neg_ex(qdev);
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}
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static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
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@ -896,33 +923,128 @@ static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
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return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
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}
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static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
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{
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printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
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/* power down device bit 11 = 1 */
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ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
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/* enable diagnostic mode bit 2 = 1 */
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ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
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/* 1000MB amplitude adjust (see Agere errata) */
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ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
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/* 1000MB amplitude adjust (see Agere errata) */
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ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
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/* 100MB amplitude adjust (see Agere errata) */
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ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
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/* 100MB amplitude adjust (see Agere errata) */
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ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
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/* 10MB amplitude adjust (see Agere errata) */
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ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
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/* 10MB amplitude adjust (see Agere errata) */
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ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
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/* point to hidden reg 0x2806 */
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ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
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/* Write new PHYAD w/bit 5 set */
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ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
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/*
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* Disable diagnostic mode bit 2 = 0
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* Power up device bit 11 = 0
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* Link up (on) and activity (blink)
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*/
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ql_mii_write_reg(qdev, 0x12, 0x840a);
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ql_mii_write_reg(qdev, 0x00, 0x1140);
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ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
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}
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static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
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u16 phyIdReg0, u16 phyIdReg1)
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{
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PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
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u32 oui;
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u16 model;
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int i;
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if (phyIdReg0 == 0xffff) {
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return result;
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}
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if (phyIdReg1 == 0xffff) {
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return result;
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}
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/* oui is split between two registers */
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oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
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model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
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/* Scan table for this PHY */
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for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
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if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
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{
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result = PHY_DEVICES[i].phyDevice;
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printk(KERN_INFO "%s: Phy: %s\n",
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qdev->ndev->name, PHY_DEVICES[i].name);
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break;
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}
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}
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return result;
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}
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static int ql_phy_get_speed(struct ql3_adapter *qdev)
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{
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u16 reg;
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switch(qdev->phyType) {
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case PHY_AGERE_ET1011C:
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{
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if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
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return 0;
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reg = (reg >> 8) & 3;
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break;
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}
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default:
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if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
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return 0;
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reg = (((reg & 0x18) >> 3) & 3);
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}
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if (reg == 2)
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switch(reg) {
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case 2:
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return SPEED_1000;
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else if (reg == 1)
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case 1:
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return SPEED_100;
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else if (reg == 0)
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case 0:
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return SPEED_10;
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else
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default:
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return -1;
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}
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}
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static int ql_is_full_dup(struct ql3_adapter *qdev)
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{
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u16 reg;
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if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
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return 0;
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return (reg & PHY_AUX_DUPLEX_STAT) != 0;
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switch(qdev->phyType) {
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case PHY_AGERE_ET1011C:
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{
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if (ql_mii_read_reg(qdev, 0x1A, ®))
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return 0;
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return ((reg & 0x0080) && (reg & 0x1000)) != 0;
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}
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case PHY_VITESSE_VSC8211:
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default:
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{
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if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
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return 0;
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return (reg & PHY_AUX_DUPLEX_STAT) != 0;
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}
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}
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}
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static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
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@ -935,6 +1057,73 @@ static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
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return (reg & PHY_NEG_PAUSE) != 0;
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}
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static int PHY_Setup(struct ql3_adapter *qdev)
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{
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u16 reg1;
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u16 reg2;
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bool agereAddrChangeNeeded = false;
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u32 miiAddr = 0;
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int err;
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/* Determine the PHY we are using by reading the ID's */
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err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
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if(err != 0) {
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printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
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qdev->ndev->name);
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return err;
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}
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err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
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if(err != 0) {
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printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
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qdev->ndev->name);
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return err;
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}
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/* Check if we have a Agere PHY */
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if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
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/* Determine which MII address we should be using
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determined by the index of the card */
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if (qdev->mac_index == 0) {
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miiAddr = MII_AGERE_ADDR_1;
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} else {
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miiAddr = MII_AGERE_ADDR_2;
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}
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err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
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if(err != 0) {
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printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
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qdev->ndev->name);
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return err;
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}
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err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
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if(err != 0) {
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printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
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qdev->ndev->name);
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return err;
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}
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/* We need to remember to initialize the Agere PHY */
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agereAddrChangeNeeded = true;
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}
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/* Determine the particular PHY we have on board to apply
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PHY specific initializations */
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qdev->phyType = getPhyType(qdev, reg1, reg2);
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if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
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/* need this here so address gets changed */
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phyAgereSpecificInit(qdev, miiAddr);
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} else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
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printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
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return -EIO;
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}
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return 0;
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}
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/*
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* Caller holds hw_lock.
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*/
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@ -1205,15 +1394,14 @@ static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
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/*
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* Caller holds hw_lock.
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*/
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static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
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u32 mac_index)
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static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
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{
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struct ql3xxx_port_registers __iomem *port_regs =
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qdev->mem_map_registers;
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u32 bitToCheck = 0;
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u32 temp;
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switch (mac_index) {
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switch (qdev->mac_index) {
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case 0:
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bitToCheck = PORT_STATUS_F1_ENABLED;
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break;
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@ -1238,27 +1426,96 @@ static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
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}
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}
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static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
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static void ql_phy_reset_ex(struct ql3_adapter *qdev)
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{
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ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
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ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
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PHYAddr[qdev->mac_index]);
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}
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static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
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static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
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{
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u16 reg;
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u16 portConfiguration;
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ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
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PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
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if(qdev->phyType == PHY_AGERE_ET1011C) {
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/* turn off external loopback */
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ql_mii_write_reg(qdev, 0x13, 0x0000);
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}
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ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, mac_index);
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ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
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mac_index);
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if(qdev->mac_index == 0)
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portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
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else
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portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
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/* Some HBA's in the field are set to 0 and they need to
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be reinterpreted with a default value */
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if(portConfiguration == 0)
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portConfiguration = PORT_CONFIG_DEFAULT;
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/* Set the 1000 advertisements */
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ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
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PHYAddr[qdev->mac_index]);
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reg &= ~PHY_GIG_ALL_PARAMS;
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if(portConfiguration &
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PORT_CONFIG_FULL_DUPLEX_ENABLED &
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PORT_CONFIG_1000MB_SPEED) {
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reg |= PHY_GIG_ADV_1000F;
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}
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if(portConfiguration &
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PORT_CONFIG_HALF_DUPLEX_ENABLED &
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PORT_CONFIG_1000MB_SPEED) {
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reg |= PHY_GIG_ADV_1000H;
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}
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ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
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PHYAddr[qdev->mac_index]);
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/* Set the 10/100 & pause negotiation advertisements */
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ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
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PHYAddr[qdev->mac_index]);
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reg &= ~PHY_NEG_ALL_PARAMS;
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if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
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reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
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if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
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if(portConfiguration & PORT_CONFIG_100MB_SPEED)
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reg |= PHY_NEG_ADV_100F;
|
||||
|
||||
if(portConfiguration & PORT_CONFIG_10MB_SPEED)
|
||||
reg |= PHY_NEG_ADV_10F;
|
||||
}
|
||||
|
||||
if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
|
||||
if(portConfiguration & PORT_CONFIG_100MB_SPEED)
|
||||
reg |= PHY_NEG_ADV_100H;
|
||||
|
||||
if(portConfiguration & PORT_CONFIG_10MB_SPEED)
|
||||
reg |= PHY_NEG_ADV_10H;
|
||||
}
|
||||
|
||||
if(portConfiguration &
|
||||
PORT_CONFIG_1000MB_SPEED) {
|
||||
reg |= 1;
|
||||
}
|
||||
|
||||
ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
|
||||
PHYAddr[qdev->mac_index]);
|
||||
|
||||
ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
|
||||
|
||||
ql_mii_write_reg_ex(qdev, CONTROL_REG,
|
||||
reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
|
||||
PHYAddr[qdev->mac_index]);
|
||||
}
|
||||
|
||||
static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
|
||||
static void ql_phy_init_ex(struct ql3_adapter *qdev)
|
||||
{
|
||||
ql_phy_reset_ex(qdev, mac_index);
|
||||
ql_phy_start_neg_ex(qdev, mac_index);
|
||||
ql_phy_reset_ex(qdev);
|
||||
PHY_Setup(qdev);
|
||||
ql_phy_start_neg_ex(qdev);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1295,14 +1552,17 @@ static int ql_port_start(struct ql3_adapter *qdev)
|
||||
{
|
||||
if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
|
||||
(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
|
||||
2) << 7))
|
||||
2) << 7)) {
|
||||
printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
|
||||
qdev->ndev->name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (ql_is_fiber(qdev)) {
|
||||
ql_petbi_init(qdev);
|
||||
} else {
|
||||
/* Copper port */
|
||||
ql_phy_init_ex(qdev, qdev->mac_index);
|
||||
ql_phy_init_ex(qdev);
|
||||
}
|
||||
|
||||
ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
|
||||
@ -1453,7 +1713,7 @@ static void ql_link_state_machine(struct ql3_adapter *qdev)
|
||||
*/
|
||||
static void ql_get_phy_owner(struct ql3_adapter *qdev)
|
||||
{
|
||||
if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
|
||||
if (ql_this_adapter_controls_port(qdev))
|
||||
set_bit(QL_LINK_MASTER,&qdev->flags);
|
||||
else
|
||||
clear_bit(QL_LINK_MASTER,&qdev->flags);
|
||||
@ -1467,11 +1727,11 @@ static void ql_init_scan_mode(struct ql3_adapter *qdev)
|
||||
ql_mii_enable_scan_mode(qdev);
|
||||
|
||||
if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
|
||||
if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
|
||||
ql_petbi_init_ex(qdev, qdev->mac_index);
|
||||
if (ql_this_adapter_controls_port(qdev))
|
||||
ql_petbi_init_ex(qdev);
|
||||
} else {
|
||||
if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
|
||||
ql_phy_init_ex(qdev, qdev->mac_index);
|
||||
if (ql_this_adapter_controls_port(qdev))
|
||||
ql_phy_init_ex(qdev);
|
||||
}
|
||||
}
|
||||
|
||||
@ -3092,6 +3352,7 @@ static int ql_adapter_initialize(struct ql3_adapter *qdev)
|
||||
goto out;
|
||||
}
|
||||
|
||||
PHY_Setup(qdev);
|
||||
ql_init_scan_mode(qdev);
|
||||
ql_get_phy_owner(qdev);
|
||||
|
||||
|
||||
@ -293,6 +293,16 @@ struct net_rsp_iocb {
|
||||
|
||||
#define MII_SCAN_REGISTER 0x00000001
|
||||
|
||||
#define PHY_ID_0_REG 2
|
||||
#define PHY_ID_1_REG 3
|
||||
|
||||
#define PHY_OUI_1_MASK 0xfc00
|
||||
#define PHY_MODEL_MASK 0x03f0
|
||||
|
||||
/* Address for the Agere Phy */
|
||||
#define MII_AGERE_ADDR_1 0x00001000
|
||||
#define MII_AGERE_ADDR_2 0x00001100
|
||||
|
||||
/* 32-bit ispControlStatus */
|
||||
enum {
|
||||
ISP_CONTROL_NP_MASK = 0x0003,
|
||||
@ -789,6 +799,7 @@ enum {
|
||||
PHY_CTRL_LOOPBACK = 0x4000,
|
||||
|
||||
PETBI_CONTROL_REG = 0x00,
|
||||
PETBI_CTRL_ALL_PARAMS = 0x7140,
|
||||
PETBI_CTRL_SOFT_RESET = 0x8000,
|
||||
PETBI_CTRL_AUTO_NEG = 0x1000,
|
||||
PETBI_CTRL_RESTART_NEG = 0x0200,
|
||||
@ -811,6 +822,23 @@ enum {
|
||||
PETBI_EXPANSION_REG = 0x06,
|
||||
PETBI_EXP_PAGE_RX = 0x0002,
|
||||
|
||||
PHY_GIG_CONTROL = 9,
|
||||
PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/
|
||||
PHY_GIG_SET_MASTER = 0x0800, /* Set Master (slave if clear)*/
|
||||
PHY_GIG_ALL_PARAMS = 0x0300,
|
||||
PHY_GIG_ADV_1000F = 0x0200,
|
||||
PHY_GIG_ADV_1000H = 0x0100,
|
||||
|
||||
PHY_NEG_ADVER = 4,
|
||||
PHY_NEG_ALL_PARAMS = 0x0fe0,
|
||||
PHY_NEG_ASY_PAUSE = 0x0800,
|
||||
PHY_NEG_SYM_PAUSE = 0x0400,
|
||||
PHY_NEG_ADV_SPEED = 0x01e0,
|
||||
PHY_NEG_ADV_100F = 0x0100,
|
||||
PHY_NEG_ADV_100H = 0x0080,
|
||||
PHY_NEG_ADV_10F = 0x0040,
|
||||
PHY_NEG_ADV_10H = 0x0020,
|
||||
|
||||
PETBI_TBI_CTRL = 0x11,
|
||||
PETBI_TBI_RESET = 0x8000,
|
||||
PETBI_TBI_AUTO_SENSE = 0x0100,
|
||||
@ -826,8 +854,7 @@ enum {
|
||||
PHY_AUX_RESET_STICK = 0x0002,
|
||||
PHY_NEG_PAUSE = 0x0400,
|
||||
PHY_CTRL_SOFT_RESET = 0x8000,
|
||||
PHY_NEG_ADVER = 4,
|
||||
PHY_NEG_ADV_SPEED = 0x01e0,
|
||||
PHY_CTRL_AUTO_NEG = 0x1000,
|
||||
PHY_CTRL_RESTART_NEG = 0x0200,
|
||||
};
|
||||
enum {
|
||||
@ -892,6 +919,7 @@ enum {EEPROM_SIZE = FM93C86A_SIZE_16,
|
||||
u16 pauseThreshold_mac;
|
||||
u16 resumeThreshold_mac;
|
||||
u16 portConfiguration;
|
||||
#define PORT_CONFIG_DEFAULT 0xf700
|
||||
#define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000
|
||||
#define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000
|
||||
#define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000
|
||||
@ -1259,6 +1287,7 @@ struct ql3_adapter {
|
||||
struct delayed_work tx_timeout_work;
|
||||
u32 max_frame_size;
|
||||
u32 device_id;
|
||||
u16 phyType;
|
||||
};
|
||||
|
||||
#endif /* _QLA3XXX_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user