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pmem: add wb_cache_pmem() to the PMEM API
__arch_wb_cache_pmem() was already an internal implementation detail of the x86 PMEM API, but this functionality needs to be exported as part of the general PMEM API to handle the fsync/msync case for DAX mmaps. One thing worth noting is that we really do want this to be part of the PMEM API as opposed to a stand-alone function like clflush_cache_range() because of ordering restrictions. By having wb_cache_pmem() as part of the PMEM API we can leave it unordered, call it multiple times to write back large amounts of memory, and then order the multiple calls with a single wmb_pmem(). Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: "J. Bruce Fields" <bfields@fieldses.org> Cc: "Theodore Ts'o" <tytso@mit.edu> Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: Andreas Dilger <adilger.kernel@dilger.ca> Cc: Dave Chinner <david@fromorbit.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jan Kara <jack@suse.com> Cc: Jeff Layton <jlayton@poochiereds.net> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Matthew Wilcox <matthew.r.wilcox@intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -67,18 +67,19 @@ static inline void arch_wmb_pmem(void)
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}
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/**
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* __arch_wb_cache_pmem - write back a cache range with CLWB
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* arch_wb_cache_pmem - write back a cache range with CLWB
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* @vaddr: virtual start address
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* @size: number of bytes to write back
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*
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* Write back a cache range using the CLWB (cache line write back)
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* instruction. This function requires explicit ordering with an
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* arch_wmb_pmem() call. This API is internal to the x86 PMEM implementation.
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* arch_wmb_pmem() call.
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*/
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static inline void __arch_wb_cache_pmem(void *vaddr, size_t size)
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static inline void arch_wb_cache_pmem(void __pmem *addr, size_t size)
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{
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u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
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unsigned long clflush_mask = x86_clflush_size - 1;
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void *vaddr = (void __force *)addr;
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void *vend = vaddr + size;
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void *p;
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@ -115,7 +116,7 @@ static inline size_t arch_copy_from_iter_pmem(void __pmem *addr, size_t bytes,
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len = copy_from_iter_nocache(vaddr, bytes, i);
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if (__iter_needs_pmem_wb(i))
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__arch_wb_cache_pmem(vaddr, bytes);
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arch_wb_cache_pmem(addr, bytes);
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return len;
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}
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@ -133,7 +134,7 @@ static inline void arch_clear_pmem(void __pmem *addr, size_t size)
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void *vaddr = (void __force *)addr;
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memset(vaddr, 0, size);
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__arch_wb_cache_pmem(vaddr, size);
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arch_wb_cache_pmem(addr, size);
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}
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static inline bool __arch_has_wmb_pmem(void)
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@ -53,12 +53,18 @@ static inline void arch_clear_pmem(void __pmem *addr, size_t size)
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{
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BUG();
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}
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static inline void arch_wb_cache_pmem(void __pmem *addr, size_t size)
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{
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BUG();
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}
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#endif
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/*
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* Architectures that define ARCH_HAS_PMEM_API must provide
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* implementations for arch_memcpy_to_pmem(), arch_wmb_pmem(),
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* arch_copy_from_iter_pmem(), arch_clear_pmem() and arch_has_wmb_pmem().
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* arch_copy_from_iter_pmem(), arch_clear_pmem(), arch_wb_cache_pmem()
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* and arch_has_wmb_pmem().
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*/
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static inline void memcpy_from_pmem(void *dst, void __pmem const *src, size_t size)
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{
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@ -178,4 +184,18 @@ static inline void clear_pmem(void __pmem *addr, size_t size)
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else
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default_clear_pmem(addr, size);
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}
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/**
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* wb_cache_pmem - write back processor cache for PMEM memory range
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* @addr: virtual start address
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* @size: number of bytes to write back
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*
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* Write back the processor cache range starting at 'addr' for 'size' bytes.
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* This function requires explicit ordering with a wmb_pmem() call.
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*/
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static inline void wb_cache_pmem(void __pmem *addr, size_t size)
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{
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if (arch_has_pmem_api())
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arch_wb_cache_pmem(addr, size);
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}
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#endif /* __PMEM_H__ */
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