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[ARM] Update Xscale and Xscale3 PTE mappings
Use 'shared device' mappings for devices, and use the standard bit combinations for Xscale3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -345,23 +345,21 @@ ENTRY(cpu_xsc3_switch_mm)
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* cpu_xsc3_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*
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*/
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cpu_xsc3_mt_table:
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.long 0x00 @ L_PTE_MT_UNCACHED
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.long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long 0x00 @ L_PTE_MT_DEV_SHARED
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.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ unused
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.long 0x00 @ L_PTE_MT_MINICACHE (not present)
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
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.long 0x00 @ unused
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long 0x00 @ L_PTE_MT_DEV_NONSHARED
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ L_PTE_MT_DEV_IXP2000 (not present)
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.long 0x00 @ unused
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.long 0x00 @ unused
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@ -434,7 +434,7 @@ cpu_xscale_mt_table:
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.long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long 0x00 @ L_PTE_MT_DEV_SHARED
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.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
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