mirror of
https://github.com/FEX-Emu/linux.git
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Merge remote-tracking branch 'asoc/topic/max98095' into asoc-next
This commit is contained in:
Mark Brown
commit
4131770d54
@ -39,6 +39,7 @@ struct max98095_cdata {
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};
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struct max98095_priv {
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struct regmap *regmap;
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enum max98095_type devtype;
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struct max98095_pdata *pdata;
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unsigned int sysclk;
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@ -56,263 +57,145 @@ struct max98095_priv {
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struct snd_soc_jack *mic_jack;
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};
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static const u8 max98095_reg_def[M98095_REG_CNT] = {
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0x00, /* 00 */
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0x00, /* 01 */
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0x00, /* 02 */
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0x00, /* 03 */
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0x00, /* 04 */
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0x00, /* 05 */
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0x00, /* 06 */
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0x00, /* 07 */
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0x00, /* 08 */
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0x00, /* 09 */
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0x00, /* 0A */
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0x00, /* 0B */
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0x00, /* 0C */
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0x00, /* 0D */
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0x00, /* 0E */
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0x00, /* 0F */
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0x00, /* 10 */
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0x00, /* 11 */
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0x00, /* 12 */
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0x00, /* 13 */
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0x00, /* 14 */
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0x00, /* 15 */
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0x00, /* 16 */
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0x00, /* 17 */
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0x00, /* 18 */
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0x00, /* 19 */
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0x00, /* 1A */
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0x00, /* 1B */
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0x00, /* 1C */
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0x00, /* 1D */
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0x00, /* 1E */
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0x00, /* 1F */
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0x00, /* 20 */
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0x00, /* 21 */
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0x00, /* 22 */
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0x00, /* 23 */
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0x00, /* 24 */
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0x00, /* 25 */
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0x00, /* 26 */
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0x00, /* 27 */
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0x00, /* 28 */
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0x00, /* 29 */
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0x00, /* 2A */
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0x00, /* 2B */
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0x00, /* 2C */
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0x00, /* 2D */
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0x00, /* 2E */
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0x00, /* 2F */
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0x00, /* 30 */
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0x00, /* 31 */
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0x00, /* 32 */
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0x00, /* 33 */
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0x00, /* 34 */
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0x00, /* 35 */
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0x00, /* 36 */
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0x00, /* 37 */
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0x00, /* 38 */
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0x00, /* 39 */
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0x00, /* 3A */
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0x00, /* 3B */
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0x00, /* 3C */
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0x00, /* 3D */
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0x00, /* 3E */
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0x00, /* 3F */
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0x00, /* 40 */
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0x00, /* 41 */
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0x00, /* 42 */
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0x00, /* 43 */
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0x00, /* 44 */
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0x00, /* 45 */
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0x00, /* 46 */
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0x00, /* 47 */
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0x00, /* 48 */
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0x00, /* 49 */
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0x00, /* 4A */
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0x00, /* 4B */
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0x00, /* 4C */
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0x00, /* 4D */
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0x00, /* 4E */
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0x00, /* 4F */
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0x00, /* 50 */
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0x00, /* 51 */
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0x00, /* 52 */
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0x00, /* 53 */
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0x00, /* 54 */
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0x00, /* 55 */
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0x00, /* 56 */
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0x00, /* 57 */
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0x00, /* 58 */
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0x00, /* 59 */
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0x00, /* 5A */
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0x00, /* 5B */
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0x00, /* 5C */
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0x00, /* 5D */
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0x00, /* 5E */
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0x00, /* 5F */
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0x00, /* 60 */
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0x00, /* 61 */
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0x00, /* 62 */
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0x00, /* 63 */
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0x00, /* 64 */
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0x00, /* 65 */
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0x00, /* 66 */
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0x00, /* 67 */
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0x00, /* 68 */
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0x00, /* 69 */
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0x00, /* 6A */
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0x00, /* 6B */
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0x00, /* 6C */
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0x00, /* 6D */
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0x00, /* 6E */
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0x00, /* 6F */
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0x00, /* 70 */
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0x00, /* 71 */
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0x00, /* 72 */
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0x00, /* 73 */
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0x00, /* 74 */
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0x00, /* 75 */
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0x00, /* 76 */
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0x00, /* 77 */
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0x00, /* 78 */
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0x00, /* 79 */
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0x00, /* 7A */
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0x00, /* 7B */
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0x00, /* 7C */
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0x00, /* 7D */
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0x00, /* 7E */
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0x00, /* 7F */
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0x00, /* 80 */
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0x00, /* 81 */
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0x00, /* 82 */
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0x00, /* 83 */
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0x00, /* 84 */
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0x00, /* 85 */
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0x00, /* 86 */
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0x00, /* 87 */
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0x00, /* 88 */
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0x00, /* 89 */
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0x00, /* 8A */
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0x00, /* 8B */
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0x00, /* 8C */
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0x00, /* 8D */
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0x00, /* 8E */
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0x00, /* 8F */
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0x00, /* 90 */
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0x00, /* 91 */
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0x30, /* 92 */
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0xF0, /* 93 */
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0x00, /* 94 */
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0x00, /* 95 */
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0x3F, /* 96 */
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0x00, /* 97 */
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0x00, /* 98 */
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0x00, /* 99 */
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0x00, /* 9A */
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0x00, /* 9B */
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0x00, /* 9C */
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0x00, /* 9D */
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0x00, /* 9E */
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0x00, /* 9F */
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0x00, /* A0 */
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0x00, /* A1 */
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0x00, /* A2 */
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0x00, /* A3 */
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0x00, /* A4 */
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0x00, /* A5 */
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0x00, /* A6 */
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0x00, /* A7 */
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0x00, /* A8 */
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0x00, /* A9 */
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0x00, /* AA */
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0x00, /* AB */
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0x00, /* AC */
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0x00, /* AD */
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0x00, /* AE */
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0x00, /* AF */
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0x00, /* B0 */
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0x00, /* B1 */
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0x00, /* B2 */
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0x00, /* B3 */
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0x00, /* B4 */
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0x00, /* B5 */
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0x00, /* B6 */
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0x00, /* B7 */
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0x00, /* B8 */
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0x00, /* B9 */
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0x00, /* BA */
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0x00, /* BB */
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0x00, /* BC */
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0x00, /* BD */
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0x00, /* BE */
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0x00, /* BF */
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0x00, /* C0 */
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0x00, /* C1 */
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0x00, /* C2 */
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0x00, /* C3 */
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0x00, /* C4 */
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0x00, /* C5 */
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0x00, /* C6 */
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0x00, /* C7 */
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0x00, /* C8 */
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0x00, /* C9 */
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0x00, /* CA */
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0x00, /* CB */
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0x00, /* CC */
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0x00, /* CD */
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0x00, /* CE */
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0x00, /* CF */
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0x00, /* D0 */
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0x00, /* D1 */
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0x00, /* D2 */
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0x00, /* D3 */
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0x00, /* D4 */
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0x00, /* D5 */
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0x00, /* D6 */
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0x00, /* D7 */
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0x00, /* D8 */
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0x00, /* D9 */
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0x00, /* DA */
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0x00, /* DB */
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0x00, /* DC */
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0x00, /* DD */
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0x00, /* DE */
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0x00, /* DF */
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0x00, /* E0 */
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0x00, /* E1 */
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0x00, /* E2 */
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0x00, /* E3 */
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0x00, /* E4 */
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0x00, /* E5 */
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0x00, /* E6 */
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0x00, /* E7 */
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0x00, /* E8 */
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0x00, /* E9 */
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0x00, /* EA */
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0x00, /* EB */
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0x00, /* EC */
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0x00, /* ED */
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0x00, /* EE */
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0x00, /* EF */
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0x00, /* F0 */
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0x00, /* F1 */
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0x00, /* F2 */
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0x00, /* F3 */
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0x00, /* F4 */
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0x00, /* F5 */
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0x00, /* F6 */
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0x00, /* F7 */
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0x00, /* F8 */
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0x00, /* F9 */
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0x00, /* FA */
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0x00, /* FB */
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0x00, /* FC */
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0x00, /* FD */
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0x00, /* FE */
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0x00, /* FF */
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static const struct reg_default max98095_reg_def[] = {
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{ 0xf, 0x00 }, /* 0F */
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{ 0x10, 0x00 }, /* 10 */
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{ 0x11, 0x00 }, /* 11 */
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{ 0x12, 0x00 }, /* 12 */
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{ 0x13, 0x00 }, /* 13 */
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{ 0x14, 0x00 }, /* 14 */
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{ 0x15, 0x00 }, /* 15 */
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{ 0x16, 0x00 }, /* 16 */
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{ 0x17, 0x00 }, /* 17 */
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{ 0x18, 0x00 }, /* 18 */
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{ 0x19, 0x00 }, /* 19 */
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{ 0x1a, 0x00 }, /* 1A */
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{ 0x1b, 0x00 }, /* 1B */
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{ 0x1c, 0x00 }, /* 1C */
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{ 0x1d, 0x00 }, /* 1D */
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{ 0x1e, 0x00 }, /* 1E */
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{ 0x1f, 0x00 }, /* 1F */
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{ 0x20, 0x00 }, /* 20 */
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{ 0x21, 0x00 }, /* 21 */
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{ 0x22, 0x00 }, /* 22 */
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{ 0x23, 0x00 }, /* 23 */
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{ 0x24, 0x00 }, /* 24 */
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{ 0x25, 0x00 }, /* 25 */
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{ 0x26, 0x00 }, /* 26 */
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{ 0x27, 0x00 }, /* 27 */
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{ 0x28, 0x00 }, /* 28 */
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{ 0x29, 0x00 }, /* 29 */
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{ 0x2a, 0x00 }, /* 2A */
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{ 0x2b, 0x00 }, /* 2B */
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{ 0x2c, 0x00 }, /* 2C */
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{ 0x2d, 0x00 }, /* 2D */
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{ 0x2e, 0x00 }, /* 2E */
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{ 0x2f, 0x00 }, /* 2F */
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{ 0x30, 0x00 }, /* 30 */
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{ 0x31, 0x00 }, /* 31 */
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{ 0x32, 0x00 }, /* 32 */
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{ 0x33, 0x00 }, /* 33 */
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{ 0x34, 0x00 }, /* 34 */
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{ 0x35, 0x00 }, /* 35 */
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{ 0x36, 0x00 }, /* 36 */
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{ 0x37, 0x00 }, /* 37 */
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{ 0x38, 0x00 }, /* 38 */
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{ 0x39, 0x00 }, /* 39 */
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{ 0x3a, 0x00 }, /* 3A */
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{ 0x3b, 0x00 }, /* 3B */
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{ 0x3c, 0x00 }, /* 3C */
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{ 0x3d, 0x00 }, /* 3D */
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{ 0x3e, 0x00 }, /* 3E */
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{ 0x3f, 0x00 }, /* 3F */
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{ 0x40, 0x00 }, /* 40 */
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{ 0x41, 0x00 }, /* 41 */
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{ 0x42, 0x00 }, /* 42 */
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{ 0x43, 0x00 }, /* 43 */
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{ 0x44, 0x00 }, /* 44 */
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{ 0x45, 0x00 }, /* 45 */
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{ 0x46, 0x00 }, /* 46 */
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{ 0x47, 0x00 }, /* 47 */
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{ 0x48, 0x00 }, /* 48 */
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{ 0x49, 0x00 }, /* 49 */
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{ 0x4a, 0x00 }, /* 4A */
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{ 0x4b, 0x00 }, /* 4B */
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{ 0x4c, 0x00 }, /* 4C */
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{ 0x4d, 0x00 }, /* 4D */
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{ 0x4e, 0x00 }, /* 4E */
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{ 0x4f, 0x00 }, /* 4F */
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{ 0x50, 0x00 }, /* 50 */
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{ 0x51, 0x00 }, /* 51 */
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{ 0x52, 0x00 }, /* 52 */
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{ 0x53, 0x00 }, /* 53 */
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{ 0x54, 0x00 }, /* 54 */
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{ 0x55, 0x00 }, /* 55 */
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{ 0x56, 0x00 }, /* 56 */
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{ 0x57, 0x00 }, /* 57 */
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{ 0x58, 0x00 }, /* 58 */
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{ 0x59, 0x00 }, /* 59 */
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{ 0x5a, 0x00 }, /* 5A */
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{ 0x5b, 0x00 }, /* 5B */
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{ 0x5c, 0x00 }, /* 5C */
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{ 0x5d, 0x00 }, /* 5D */
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{ 0x5e, 0x00 }, /* 5E */
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{ 0x5f, 0x00 }, /* 5F */
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{ 0x60, 0x00 }, /* 60 */
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{ 0x61, 0x00 }, /* 61 */
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{ 0x62, 0x00 }, /* 62 */
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{ 0x63, 0x00 }, /* 63 */
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||||
{ 0x64, 0x00 }, /* 64 */
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{ 0x65, 0x00 }, /* 65 */
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||||
{ 0x66, 0x00 }, /* 66 */
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{ 0x67, 0x00 }, /* 67 */
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||||
{ 0x68, 0x00 }, /* 68 */
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{ 0x69, 0x00 }, /* 69 */
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{ 0x6a, 0x00 }, /* 6A */
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{ 0x6b, 0x00 }, /* 6B */
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{ 0x6c, 0x00 }, /* 6C */
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||||
{ 0x6d, 0x00 }, /* 6D */
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||||
{ 0x6e, 0x00 }, /* 6E */
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||||
{ 0x6f, 0x00 }, /* 6F */
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||||
{ 0x70, 0x00 }, /* 70 */
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{ 0x71, 0x00 }, /* 71 */
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{ 0x72, 0x00 }, /* 72 */
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{ 0x73, 0x00 }, /* 73 */
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||||
{ 0x74, 0x00 }, /* 74 */
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||||
{ 0x75, 0x00 }, /* 75 */
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||||
{ 0x76, 0x00 }, /* 76 */
|
||||
{ 0x77, 0x00 }, /* 77 */
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{ 0x78, 0x00 }, /* 78 */
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||||
{ 0x79, 0x00 }, /* 79 */
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{ 0x7a, 0x00 }, /* 7A */
|
||||
{ 0x7b, 0x00 }, /* 7B */
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{ 0x7c, 0x00 }, /* 7C */
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||||
{ 0x7d, 0x00 }, /* 7D */
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||||
{ 0x7e, 0x00 }, /* 7E */
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||||
{ 0x7f, 0x00 }, /* 7F */
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||||
{ 0x80, 0x00 }, /* 80 */
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||||
{ 0x81, 0x00 }, /* 81 */
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||||
{ 0x82, 0x00 }, /* 82 */
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||||
{ 0x83, 0x00 }, /* 83 */
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||||
{ 0x84, 0x00 }, /* 84 */
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||||
{ 0x85, 0x00 }, /* 85 */
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||||
{ 0x86, 0x00 }, /* 86 */
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||||
{ 0x87, 0x00 }, /* 87 */
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||||
{ 0x88, 0x00 }, /* 88 */
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{ 0x89, 0x00 }, /* 89 */
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||||
{ 0x8a, 0x00 }, /* 8A */
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||||
{ 0x8b, 0x00 }, /* 8B */
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||||
{ 0x8c, 0x00 }, /* 8C */
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||||
{ 0x8d, 0x00 }, /* 8D */
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||||
{ 0x8e, 0x00 }, /* 8E */
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||||
{ 0x8f, 0x00 }, /* 8F */
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||||
{ 0x90, 0x00 }, /* 90 */
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||||
{ 0x91, 0x00 }, /* 91 */
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||||
{ 0x92, 0x30 }, /* 92 */
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||||
{ 0x93, 0xF0 }, /* 93 */
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||||
{ 0x94, 0x00 }, /* 94 */
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||||
{ 0x95, 0x00 }, /* 95 */
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||||
{ 0x96, 0x3F }, /* 96 */
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||||
{ 0x97, 0x00 }, /* 97 */
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||||
{ 0xff, 0x00 }, /* FF */
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||||
};
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||||
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||||
static struct {
|
||||
@ -577,14 +460,14 @@ static struct {
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||||
{ 0xFF, 0x00 }, /* FF */
|
||||
};
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||||
|
||||
static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg)
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||||
static bool max98095_readable(struct device *dev, unsigned int reg)
|
||||
{
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||||
if (reg >= M98095_REG_CNT)
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return 0;
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||||
return max98095_access[reg].readable != 0;
|
||||
}
|
||||
|
||||
static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg)
|
||||
static bool max98095_volatile(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg > M98095_REG_MAX_CACHED)
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||||
return 1;
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||||
@ -611,22 +494,18 @@ static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg)
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||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Filter coefficients are in a separate register segment
|
||||
* and they share the address space of the normal registers.
|
||||
* The coefficient registers do not need or share the cache.
|
||||
*/
|
||||
static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg,
|
||||
unsigned int value)
|
||||
{
|
||||
int ret;
|
||||
static const struct regmap_config max98095_regmap = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
|
||||
codec->cache_bypass = 1;
|
||||
ret = snd_soc_write(codec, reg, value);
|
||||
codec->cache_bypass = 0;
|
||||
.reg_defaults = max98095_reg_def,
|
||||
.num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
|
||||
.max_register = M98095_0FF_REV_ID,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
|
||||
return ret ? -EIO : 0;
|
||||
}
|
||||
.readable_reg = max98095_readable,
|
||||
.volatile_reg = max98095_volatile,
|
||||
};
|
||||
|
||||
/*
|
||||
* Load equalizer DSP coefficient configurations registers
|
||||
@ -648,8 +527,8 @@ static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
|
||||
|
||||
/* Step through the registers and coefs */
|
||||
for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
|
||||
max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
|
||||
max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
|
||||
snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
|
||||
snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
|
||||
}
|
||||
}
|
||||
|
||||
@ -673,8 +552,8 @@ static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
|
||||
|
||||
/* Step through the registers and coefs */
|
||||
for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
|
||||
max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
|
||||
max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
|
||||
snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
|
||||
snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
|
||||
}
|
||||
}
|
||||
|
||||
@ -1285,14 +1164,6 @@ static const struct snd_soc_dapm_route max98095_audio_map[] = {
|
||||
{"MIC2 Input", NULL, "MIC2"},
|
||||
};
|
||||
|
||||
static int max98095_add_widgets(struct snd_soc_codec *codec)
|
||||
{
|
||||
snd_soc_add_codec_controls(codec, max98095_snd_controls,
|
||||
ARRAY_SIZE(max98095_snd_controls));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* codec mclk clock divider coefficients */
|
||||
static const struct {
|
||||
u32 rate;
|
||||
@ -1748,6 +1619,7 @@ static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
|
||||
static int max98095_set_bias_level(struct snd_soc_codec *codec,
|
||||
enum snd_soc_bias_level level)
|
||||
{
|
||||
struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
|
||||
int ret;
|
||||
|
||||
switch (level) {
|
||||
@ -1759,7 +1631,7 @@ static int max98095_set_bias_level(struct snd_soc_codec *codec,
|
||||
|
||||
case SND_SOC_BIAS_STANDBY:
|
||||
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
|
||||
ret = snd_soc_cache_sync(codec);
|
||||
ret = regcache_sync(max98095->regmap);
|
||||
|
||||
if (ret != 0) {
|
||||
dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
|
||||
@ -1774,7 +1646,7 @@ static int max98095_set_bias_level(struct snd_soc_codec *codec,
|
||||
case SND_SOC_BIAS_OFF:
|
||||
snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
|
||||
M98095_MBEN, 0);
|
||||
codec->cache_sync = 1;
|
||||
regcache_mark_dirty(max98095->regmap);
|
||||
break;
|
||||
}
|
||||
codec->dapm.bias_level = level;
|
||||
@ -2341,7 +2213,7 @@ static int max98095_reset(struct snd_soc_codec *codec)
|
||||
/* Reset to hardware default for registers, as there is not
|
||||
* a soft reset hardware control register */
|
||||
for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
|
||||
ret = snd_soc_write(codec, i, max98095_reg_def[i]);
|
||||
ret = snd_soc_write(codec, i, snd_soc_read(codec, i));
|
||||
if (ret < 0) {
|
||||
dev_err(codec->dev, "Failed to reset: %d\n", ret);
|
||||
return ret;
|
||||
@ -2358,7 +2230,7 @@ static int max98095_probe(struct snd_soc_codec *codec)
|
||||
struct i2c_client *client;
|
||||
int ret = 0;
|
||||
|
||||
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
|
||||
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
|
||||
if (ret != 0) {
|
||||
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
|
||||
return ret;
|
||||
@ -2447,8 +2319,6 @@ static int max98095_probe(struct snd_soc_codec *codec)
|
||||
snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
|
||||
M98095_SHDNRUN);
|
||||
|
||||
max98095_add_widgets(codec);
|
||||
|
||||
return 0;
|
||||
|
||||
err_irq:
|
||||
@ -2480,11 +2350,8 @@ static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
|
||||
.suspend = max98095_suspend,
|
||||
.resume = max98095_resume,
|
||||
.set_bias_level = max98095_set_bias_level,
|
||||
.reg_cache_size = ARRAY_SIZE(max98095_reg_def),
|
||||
.reg_word_size = sizeof(u8),
|
||||
.reg_cache_default = max98095_reg_def,
|
||||
.readable_register = max98095_readable,
|
||||
.volatile_register = max98095_volatile,
|
||||
.controls = max98095_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(max98095_snd_controls),
|
||||
.dapm_widgets = max98095_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
|
||||
.dapm_routes = max98095_audio_map,
|
||||
@ -2502,6 +2369,13 @@ static int max98095_i2c_probe(struct i2c_client *i2c,
|
||||
if (max98095 == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
|
||||
if (IS_ERR(max98095->regmap)) {
|
||||
ret = PTR_ERR(max98095->regmap);
|
||||
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
max98095->devtype = id->driver_data;
|
||||
i2c_set_clientdata(i2c, max98095);
|
||||
max98095->pdata = i2c->dev.platform_data;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user