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ALSA: hda/ca0132 - Add DSP setup functions for AE-5
This patch adds DSP setup functions for the AE-5. Signed-off-by: Connor McAdams <conmanx360@gmail.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Connor McAdams
Takashi Iwai
parent
6ef0e91ec4
commit
415cd8447c
@ -6524,6 +6524,151 @@ static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
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}
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}
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static void ae5_post_dsp_register_set(struct hda_codec *codec)
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{
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struct ca0132_spec *spec = codec->spec;
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chipio_8051_write_direct(codec, 0x93, 0x10);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0x00, spec->mem_base + 0x100);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0x00, spec->mem_base + 0x100);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0x00, spec->mem_base + 0x100);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0x00, spec->mem_base + 0x100);
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writeb(0xff, spec->mem_base + 0x304);
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ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
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ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
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ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
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}
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static void ae5_post_dsp_param_setup(struct hda_codec *codec)
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{
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/*
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* Param3 in the 8051's memory is represented by the ascii string 'mch'
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* which seems to be 'multichannel'. This is also mentioned in the
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* AE-5's registry values in Windows.
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*/
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chipio_set_control_param(codec, 3, 0);
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/*
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* I believe ASI is 'audio serial interface' and that it's used to
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* change colors on the external LED strip connected to the AE-5.
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*/
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chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
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chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
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}
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static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
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{
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
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}
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static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
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{
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struct ca0132_spec *spec = codec->spec;
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mutex_lock(&spec->chipio_mutex);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
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chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
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chipio_set_stream_channels(codec, 0x0C, 6);
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chipio_set_stream_control(codec, 0x0C, 1);
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chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
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chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
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chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
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chipio_set_stream_channels(codec, 0x18, 6);
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chipio_set_stream_control(codec, 0x18, 1);
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chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
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ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
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mutex_unlock(&spec->chipio_mutex);
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}
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static void ae5_post_dsp_startup_data(struct hda_codec *codec)
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{
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struct ca0132_spec *spec = codec->spec;
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mutex_lock(&spec->chipio_mutex);
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chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
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chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
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chipio_write_no_mutex(codec, 0x189024, 0x00014004);
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chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
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ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
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chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
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ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
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ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
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ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
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ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
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ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
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ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
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ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
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ca0113_mmio_gpio_set(codec, 0, true);
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ca0113_mmio_gpio_set(codec, 1, true);
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ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
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chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
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ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
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ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
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mutex_unlock(&spec->chipio_mutex);
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}
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/*
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* Setup default parameters for DSP
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*/
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@ -6670,6 +6815,73 @@ static void sbz_setup_defaults(struct hda_codec *codec)
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ca0132_alt_create_dummy_stream(codec);
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}
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/*
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* Setup default parameters for the Sound BlasterX AE-5 DSP.
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*/
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static void ae5_setup_defaults(struct hda_codec *codec)
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{
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struct ca0132_spec *spec = codec->spec;
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unsigned int tmp;
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int num_fx;
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int idx, i;
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if (spec->dsp_state != DSP_DOWNLOADED)
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return;
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ca0132_alt_dsp_scp_startup(codec);
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ca0132_alt_init_analog_mics(codec);
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chipio_set_stream_control(codec, 0x03, 1);
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chipio_set_stream_control(codec, 0x04, 1);
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/* New, unknown SCP req's */
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tmp = FLOAT_ZERO;
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dspio_set_uint_param(codec, 0x96, 0x29, tmp);
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dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
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dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
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dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
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ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
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ca0113_mmio_gpio_set(codec, 0, false);
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ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
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/* Internal loopback off */
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tmp = FLOAT_ONE;
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dspio_set_uint_param(codec, 0x37, 0x08, tmp);
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dspio_set_uint_param(codec, 0x37, 0x10, tmp);
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/*remove DSP headroom*/
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tmp = FLOAT_ZERO;
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dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
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/* set WUH source */
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tmp = FLOAT_TWO;
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dspio_set_uint_param(codec, 0x31, 0x00, tmp);
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chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
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/* Set speaker source? */
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dspio_set_uint_param(codec, 0x32, 0x00, tmp);
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ca0132_alt_dsp_initial_mic_setup(codec);
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ae5_post_dsp_register_set(codec);
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ae5_post_dsp_param_setup(codec);
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ae5_post_dsp_pll_setup(codec);
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ae5_post_dsp_stream_setup(codec);
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ae5_post_dsp_startup_data(codec);
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/* out, in effects + voicefx */
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num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
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for (idx = 0; idx < num_fx; idx++) {
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for (i = 0; i <= ca0132_effects[idx].params; i++) {
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dspio_set_uint_param(codec,
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ca0132_effects[idx].mid,
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ca0132_effects[idx].reqs[i],
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ca0132_effects[idx].def_vals[i]);
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}
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}
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ca0132_alt_create_dummy_stream(codec);
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}
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/*
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* Initialization of flags in chip
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*/
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@ -7490,6 +7702,9 @@ static int ca0132_init(struct hda_codec *codec)
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case QUIRK_SBZ:
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sbz_setup_defaults(codec);
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break;
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case QUIRK_AE5:
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ae5_setup_defaults(codec);
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break;
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default:
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ca0132_setup_defaults(codec);
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ca0132_init_analog_mic2(codec);
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