From 28c039eebaaa28def9364b9a12a30192be8b4730 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Thu, 15 Oct 2015 20:28:46 +0200 Subject: [PATCH 1/2] ARM: berlin: dts: add CLKID_CPU for BG2Q Marvell Berlin BG2Q SoC also has a clock for the CPU, add a corresponding CLKID to the dt-binding include. Signed-off-by: Antoine Tenart Signed-off-by: Sebastian Hesselbarth --- include/dt-bindings/clock/berlin2q.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/berlin2q.h b/include/dt-bindings/clock/berlin2q.h index 287fc3b4afb2..72eaf91c9ca6 100644 --- a/include/dt-bindings/clock/berlin2q.h +++ b/include/dt-bindings/clock/berlin2q.h @@ -29,3 +29,4 @@ #define CLKID_SMEMC 24 #define CLKID_PCIE 25 #define CLKID_TWD 26 +#define CLKID_CPU 27 From 515f1a2027006839c08c842da919abfcc3c7ae2a Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 15 Oct 2015 20:55:55 +0200 Subject: [PATCH 2/2] clk: berlin: add cpuclk Add cpuclk in the Berlin BG2Q clock driver. This clk has a divider fixed to 1. Signed-off-by: Antoine Tenart Acked-by: Stephen Boyd Signed-off-by: Sebastian Hesselbarth --- drivers/clk/berlin/bg2q.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c index 221f40c2b850..72d2f3500db8 100644 --- a/drivers/clk/berlin/bg2q.c +++ b/drivers/clk/berlin/bg2q.c @@ -45,7 +45,7 @@ #define REG_SDIO0XIN_CLKCTL 0x0158 #define REG_SDIO1XIN_CLKCTL 0x015c -#define MAX_CLKS 27 +#define MAX_CLKS 28 static struct clk *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); @@ -356,13 +356,13 @@ static void __init berlin2q_clock_setup(struct device_node *np) gd->bit_idx, 0, &lock); } - /* - * twdclk is derived from cpu/3 - * TODO: use cpupll until cpuclk is not available - */ + /* cpuclk divider is fixed to 1 */ + clks[CLKID_CPU] = + clk_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL], + 0, 1, 1); + /* twdclk is derived from cpu/3 */ clks[CLKID_TWD] = - clk_register_fixed_factor(NULL, "twd", clk_names[CPUPLL], - 0, 1, 3); + clk_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3); /* check for errors on leaf clocks */ for (n = 0; n < MAX_CLKS; n++) {