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drm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xx
Print various CP register that have valuable informations regarding GPU lockup. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -2316,6 +2316,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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@ -2353,6 +2361,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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evergreen_mc_resume(rdev, &save);
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return 0;
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}
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@ -88,6 +88,10 @@
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#define CONFIG_MEMSIZE 0x5428
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#define CP_COHER_BASE 0x85F8
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#define CP_STALLED_STAT1 0x8674
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#define CP_STALLED_STAT2 0x8678
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#define CP_BUSY_STAT 0x867C
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#define CP_STAT 0x8680
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#define CP_ME_CNTL 0x86D8
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#define CP_ME_HALT (1 << 28)
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#define CP_PFP_HALT (1 << 26)
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@ -1122,6 +1122,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(0x14F8));
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dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
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@ -1170,6 +1178,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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evergreen_mc_resume(rdev, &save);
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return 0;
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}
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@ -236,6 +236,10 @@
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#define CP_SEM_WAIT_TIMER 0x85BC
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#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
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#define CP_COHER_CNTL2 0x85E8
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#define CP_STALLED_STAT1 0x8674
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#define CP_STALLED_STAT2 0x8678
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#define CP_BUSY_STAT 0x867C
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#define CP_STAT 0x8680
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#define CP_ME_CNTL 0x86D8
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#define CP_ME_HALT (1 << 28)
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#define CP_PFP_HALT (1 << 26)
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@ -1289,6 +1289,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(R_008014_GRBM_STATUS2));
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
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RREG32(R_000E50_SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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rv515_mc_stop(rdev, &save);
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if (r600_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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@ -1332,6 +1340,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(R_008014_GRBM_STATUS2));
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
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RREG32(R_000E50_SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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rv515_mc_resume(rdev, &save);
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return 0;
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}
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@ -153,6 +153,9 @@
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#define CONFIG_MEMSIZE 0x5428
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#define CONFIG_CNTL 0x5424
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#define CP_STALLED_STAT1 0x8674
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#define CP_STALLED_STAT2 0x8678
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#define CP_BUSY_STAT 0x867C
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#define CP_STAT 0x8680
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#define CP_COHER_BASE 0x85F8
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#define CP_DEBUG 0xC1FC
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