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RDMA/cxgb3: Support version 5.0 firmware
The 5.0 firmware now supports translating sgls in recv work requests, so remove the host driver logic currently doing the translation. Note: this change requires 5.0 firmware. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -208,36 +208,19 @@ static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
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static int iwch_build_rdma_recv(struct iwch_dev *rhp, union t3_wr *wqe,
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struct ib_recv_wr *wr)
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{
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int i, err = 0;
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u32 pbl_addr[4];
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u8 page_size[4];
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int i;
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if (wr->num_sge > T3_MAX_SGE)
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return -EINVAL;
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err = iwch_sgl2pbl_map(rhp, wr->sg_list, wr->num_sge, pbl_addr,
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page_size);
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if (err)
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return err;
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wqe->recv.pagesz[0] = page_size[0];
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wqe->recv.pagesz[1] = page_size[1];
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wqe->recv.pagesz[2] = page_size[2];
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wqe->recv.pagesz[3] = page_size[3];
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wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
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for (i = 0; i < wr->num_sge; i++) {
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wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
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wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
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/* to in the WQE == the offset into the page */
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wqe->recv.sgl[i].to = cpu_to_be64(((u32) wr->sg_list[i].addr) %
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(1UL << (12 + page_size[i])));
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/* pbl_addr is the adapters address in the PBL */
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wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
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wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
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}
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for (; i < T3_MAX_SGE; i++) {
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wqe->recv.sgl[i].stag = 0;
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wqe->recv.sgl[i].len = 0;
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wqe->recv.sgl[i].to = 0;
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wqe->recv.pbl_addr[i] = 0;
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}
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return 0;
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}
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