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[media] davinci: vpfe: dm365: resizer driver based on media framework
Add the video resizer driver with the v4l2 media controller framework which takes care of resizing the video frames with both up-scaling downscaling facility. The driver supports both continuous and single shot operations.The driver supports resizer as a subdevice and a media entity. It has support for 2 resizers - resizerA and resizerB. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Sakari Ailus <sakari.ailus@iki.fi> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Manjunath Hadli
Mauro Carvalho Chehab
parent
26c0e9992c
commit
45e46b3bbe
1999
drivers/staging/media/davinci_vpfe/dm365_resizer.c
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1999
drivers/staging/media/davinci_vpfe/dm365_resizer.c
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244
drivers/staging/media/davinci_vpfe/dm365_resizer.h
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drivers/staging/media/davinci_vpfe/dm365_resizer.h
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/*
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* Copyright (C) 2012 Texas Instruments Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Contributors:
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* Manjunath Hadli <manjunath.hadli@ti.com>
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* Prabhakar Lad <prabhakar.lad@ti.com>
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*/
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#ifndef _DAVINCI_VPFE_DM365_RESIZER_H
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#define _DAVINCI_VPFE_DM365_RESIZER_H
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enum resizer_oper_mode {
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RESIZER_MODE_CONTINIOUS = 0,
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RESIZER_MODE_ONE_SHOT = 1,
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};
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struct f_div_pass {
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unsigned int o_hsz;
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unsigned int i_hps;
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unsigned int h_phs;
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unsigned int src_hps;
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unsigned int src_hsz;
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};
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#define MAX_PASSES 2
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struct f_div_param {
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unsigned char en;
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unsigned int num_passes;
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struct f_div_pass pass[MAX_PASSES];
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};
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/* Resizer Rescale Parameters*/
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struct resizer_scale_param {
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bool h_flip;
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bool v_flip;
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bool cen;
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bool yen;
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unsigned short i_vps;
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unsigned short i_hps;
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unsigned short o_vsz;
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unsigned short o_hsz;
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unsigned short v_phs_y;
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unsigned short v_phs_c;
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unsigned short v_dif;
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/* resize method - Luminance */
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enum vpfe_rsz_intp_t v_typ_y;
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/* resize method - Chrominance */
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enum vpfe_rsz_intp_t v_typ_c;
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/* vertical lpf intensity - Luminance */
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unsigned char v_lpf_int_y;
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/* vertical lpf intensity - Chrominance */
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unsigned char v_lpf_int_c;
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unsigned short h_phs;
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unsigned short h_dif;
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/* resize method - Luminance */
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enum vpfe_rsz_intp_t h_typ_y;
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/* resize method - Chrominance */
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enum vpfe_rsz_intp_t h_typ_c;
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/* horizontal lpf intensity - Luminance */
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unsigned char h_lpf_int_y;
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/* horizontal lpf intensity - Chrominance */
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unsigned char h_lpf_int_c;
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bool dscale_en;
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enum vpfe_rsz_down_scale_ave_sz h_dscale_ave_sz;
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enum vpfe_rsz_down_scale_ave_sz v_dscale_ave_sz;
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/* store the calculated frame division parameter */
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struct f_div_param f_div;
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};
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enum resizer_rgb_t {
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OUTPUT_32BIT,
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OUTPUT_16BIT
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};
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enum resizer_rgb_msk_t {
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NOMASK = 0,
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MASKLAST2 = 1,
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};
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/* Resizer RGB Conversion Parameters */
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struct resizer_rgb {
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bool rgb_en;
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enum resizer_rgb_t rgb_typ;
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enum resizer_rgb_msk_t rgb_msk0;
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enum resizer_rgb_msk_t rgb_msk1;
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unsigned int rgb_alpha_val;
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};
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/* Resizer External Memory Parameters */
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struct rsz_ext_mem_param {
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unsigned int rsz_sdr_oft_y;
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unsigned int rsz_sdr_ptr_s_y;
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unsigned int rsz_sdr_ptr_e_y;
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unsigned int rsz_sdr_oft_c;
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unsigned int rsz_sdr_ptr_s_c;
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unsigned int rsz_sdr_ptr_e_c;
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/* offset to be added to buffer start when flipping for y/ycbcr */
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unsigned int flip_ofst_y;
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/* offset to be added to buffer start when flipping for c */
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unsigned int flip_ofst_c;
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/* c offset for YUV 420SP */
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unsigned int c_offset;
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/* User Defined Y offset for YUV 420SP or YUV420ILE data */
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unsigned int user_y_ofst;
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/* User Defined C offset for YUV 420SP data */
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unsigned int user_c_ofst;
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};
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enum rsz_data_source {
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IPIPE_DATA,
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IPIPEIF_DATA
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};
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enum rsz_src_img_fmt {
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RSZ_IMG_422,
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RSZ_IMG_420
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};
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enum rsz_dpaths_bypass_t {
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BYPASS_OFF = 0,
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BYPASS_ON = 1,
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};
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struct rsz_common_params {
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unsigned int vps;
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unsigned int vsz;
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unsigned int hps;
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unsigned int hsz;
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/* 420 or 422 */
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enum rsz_src_img_fmt src_img_fmt;
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/* Y or C when src_fmt is 420, 0 - y, 1 - c */
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unsigned char y_c;
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/* flip raw or ycbcr */
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unsigned char raw_flip;
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/* IPIPE or IPIPEIF data */
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enum rsz_data_source source;
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enum rsz_dpaths_bypass_t passthrough;
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unsigned char yuv_y_min;
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unsigned char yuv_y_max;
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unsigned char yuv_c_min;
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unsigned char yuv_c_max;
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bool rsz_seq_crv;
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enum vpfe_chr_pos out_chr_pos;
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};
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struct resizer_params {
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enum resizer_oper_mode oper_mode;
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struct rsz_common_params rsz_common;
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struct resizer_scale_param rsz_rsc_param[2];
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struct resizer_rgb rsz2rgb[2];
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struct rsz_ext_mem_param ext_mem_param[2];
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bool rsz_en[2];
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struct vpfe_rsz_config_params user_config;
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};
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#define ENABLE 1
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#define DISABLE (!ENABLE)
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#define RESIZER_CROP_PAD_SINK 0
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#define RESIZER_CROP_PAD_SOURCE 1
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#define RESIZER_CROP_PAD_SOURCE2 2
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#define RESIZER_CROP_PADS_NUM 3
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enum resizer_crop_input_entity {
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RESIZER_CROP_INPUT_NONE = 0,
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RESIZER_CROP_INPUT_IPIPEIF = 1,
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RESIZER_CROP_INPUT_IPIPE = 2,
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};
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enum resizer_crop_output_entity {
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RESIZER_CROP_OUTPUT_NONE,
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RESIZER_A,
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RESIZER_B,
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};
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struct dm365_crop_resizer_device {
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struct v4l2_subdev subdev;
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struct media_pad pads[RESIZER_CROP_PADS_NUM];
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struct v4l2_mbus_framefmt formats[RESIZER_CROP_PADS_NUM];
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enum resizer_crop_input_entity input;
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enum resizer_crop_output_entity output;
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enum resizer_crop_output_entity output2;
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struct vpfe_resizer_device *rsz_device;
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};
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#define RESIZER_PAD_SINK 0
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#define RESIZER_PAD_SOURCE 1
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#define RESIZER_PADS_NUM 2
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enum resizer_input_entity {
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RESIZER_INPUT_NONE = 0,
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RESIZER_INPUT_CROP_RESIZER = 1,
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};
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enum resizer_output_entity {
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RESIZER_OUTPUT_NONE = 0,
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RESIZER_OUPUT_MEMORY = 1,
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};
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struct dm365_resizer_device {
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struct v4l2_subdev subdev;
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struct media_pad pads[RESIZER_PADS_NUM];
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struct v4l2_mbus_framefmt formats[RESIZER_PADS_NUM];
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enum resizer_input_entity input;
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enum resizer_output_entity output;
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struct vpfe_video_device video_out;
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struct vpfe_resizer_device *rsz_device;
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};
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struct vpfe_resizer_device {
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struct dm365_crop_resizer_device crop_resizer;
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struct dm365_resizer_device resizer_a;
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struct dm365_resizer_device resizer_b;
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struct resizer_params config;
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void *__iomem base_addr;
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};
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int vpfe_resizer_init(struct vpfe_resizer_device *vpfe_rsz,
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struct platform_device *pdev);
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int vpfe_resizer_register_entities(struct vpfe_resizer_device *vpfe_rsz,
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struct v4l2_device *v4l2_dev);
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void vpfe_resizer_unregister_entities(struct vpfe_resizer_device *vpfe_rsz);
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void vpfe_resizer_cleanup(struct vpfe_resizer_device *vpfe_rsz,
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struct platform_device *pdev);
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void vpfe_resizer_buffer_isr(struct vpfe_resizer_device *resizer);
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void vpfe_resizer_dma_isr(struct vpfe_resizer_device *resizer);
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#endif /* _DAVINCI_VPFE_DM365_RESIZER_H */
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