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clk: samsung: exynos5433: Add clocks for CMU_HEVC domain
This patch adds the mux/divider/gate clocks for CMU_HEVC domain which generates the clocks for HEVC(High Efficiency Video Codec) decoder IP. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
Sylwester Nawrocki
parent
9910b6bbaa
commit
45e58aa5f7
@ -41,6 +41,8 @@ Required Properties:
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which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
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- "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
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which generates clocks for MFC(Multi-Format Codec) IP.
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- "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
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which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -131,6 +133,10 @@ Required Properties:
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- oscclk
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- aclk_mfc_400
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Input clocks for hevc clock controller:
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- oscclk
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- aclk_hevc_400
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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@ -355,6 +361,15 @@ Example 2: Examples of clock controller nodes are listed below.
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clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
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};
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cmu_hevc: clock-controller@14f80000 {
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compatible = "samsung,exynos5433-cmu-hevc";
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reg = <0x14f80000 0x0b08>;
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#clock-cells = <1>;
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clock-names = "oscclk", "aclk_hevc_400";
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clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
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};
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Example 3: UART controller node that consumes the clock generated by the clock
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controller.
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@ -560,6 +560,9 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
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GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
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ENABLE_ACLK_TOP, 14,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
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ENABLE_ACLK_TOP, 5,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
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ENABLE_ACLK_TOP, 3,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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@ -4103,3 +4106,115 @@ static void __init exynos5433_cmu_mfc_init(struct device_node *np)
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}
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CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
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exynos5433_cmu_mfc_init);
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/*
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* Register offset definitions for CMU_HEVC
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*/
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#define MUX_SEL_HEVC 0x0200
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#define MUX_ENABLE_HEVC 0x0300
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#define MUX_STAT_HEVC 0x0400
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#define DIV_HEVC 0x0600
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#define DIV_STAT_HEVC 0x0700
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#define ENABLE_ACLK_HEVC 0x0800
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#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
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#define ENABLE_PCLK_HEVC 0x0900
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#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
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#define ENABLE_IP_HEVC0 0x0b00
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#define ENABLE_IP_HEVC1 0x0b04
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#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
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static unsigned long hevc_clk_regs[] __initdata = {
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MUX_SEL_HEVC,
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MUX_ENABLE_HEVC,
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MUX_STAT_HEVC,
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DIV_HEVC,
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DIV_STAT_HEVC,
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ENABLE_ACLK_HEVC,
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ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
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ENABLE_PCLK_HEVC,
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ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
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ENABLE_IP_HEVC0,
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ENABLE_IP_HEVC1,
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ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
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};
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PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
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static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
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/* MUX_SEL_HEVC */
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MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
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mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
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};
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static struct samsung_div_clock hevc_div_clks[] __initdata = {
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/* DIV_HEVC */
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DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
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DIV_HEVC, 0, 2),
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};
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static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
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/* ENABLE_ACLK_HEVC */
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GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
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ENABLE_ACLK_HEVC, 6, 0, 0),
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GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
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ENABLE_ACLK_HEVC, 5, 0, 0),
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GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
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ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
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ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
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ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
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ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
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ENABLE_ACLK_HEVC, 0, 0, 0),
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/* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
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GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
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"mout_aclk_hevc_400_user",
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ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
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1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
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"mout_aclk_hevc_400_user",
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ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_HEVC */
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GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
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ENABLE_PCLK_HEVC, 4, 0, 0),
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GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
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ENABLE_PCLK_HEVC, 3, 0, 0),
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GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
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ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
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ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
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ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
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GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
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ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
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1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
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ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
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0, CLK_IGNORE_UNUSED, 0),
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};
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static struct samsung_cmu_info hevc_cmu_info __initdata = {
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.mux_clks = hevc_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
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.div_clks = hevc_div_clks,
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.nr_div_clks = ARRAY_SIZE(hevc_div_clks),
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.gate_clks = hevc_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
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.nr_clk_ids = HEVC_NR_CLK,
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.clk_regs = hevc_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
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};
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static void __init exynos5433_cmu_hevc_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &hevc_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
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exynos5433_cmu_hevc_init);
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@ -154,8 +154,9 @@
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#define CLK_SCLK_JPEG_MSCL 234
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#define CLK_ACLK_MSCL_400 235
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#define CLK_ACLK_MFC_400 236
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#define CLK_ACLK_HEVC_400 237
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#define TOP_NR_CLK 237
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#define TOP_NR_CLK 238
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/* CMU_CPIF */
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#define CLK_FOUT_MPHY_PLL 1
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@ -1001,4 +1002,28 @@
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#define MFC_NR_CLK 19
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/* CMU_HEVC */
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#define CLK_MOUT_ACLK_HEVC_400_USER 1
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#define CLK_DIV_PCLK_HEVC 2
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#define CLK_ACLK_BTS_HEVC_1 3
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#define CLK_ACLK_BTS_HEVC_0 4
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#define CLK_ACLK_AHB2APB_HEVCP 5
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#define CLK_ACLK_XIU_HEVCX 6
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#define CLK_ACLK_HEVCNP_100 7
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#define CLK_ACLK_HEVCND_400 8
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#define CLK_ACLK_HEVC 9
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#define CLK_ACLK_SMMU_HEVC_1 10
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#define CLK_ACLK_SMMU_HEVC_0 11
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#define CLK_PCLK_BTS_HEVC_1 12
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#define CLK_PCLK_BTS_HEVC_0 13
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#define CLK_PCLK_PMU_HEVC 14
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#define CLK_PCLK_SYSREG_HEVC 15
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#define CLK_PCLK_HEVC 16
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#define CLK_PCLK_SMMU_HEVC_1 17
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#define CLK_PCLK_SMMU_HEVC_0 18
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#define HEVC_NR_CLK 19
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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