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ARM: shmobile: apmu: Add more register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -31,9 +31,15 @@ static struct {
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int bit;
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int bit;
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} apmu_cpus[NR_CPUS];
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} apmu_cpus[NR_CPUS];
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#define WUPCR_OFFS 0x10
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#define WUPCR_OFFS 0x10 /* Wake Up Control Register */
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#define PSTR_OFFS 0x40
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#define PSTR_OFFS 0x40 /* Power Status Register */
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#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
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#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
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/* CPUn Power Status Control Register */
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/* Power Status Register */
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#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */
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#define CPUST_RUN 0 /* Run Mode */
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#define CPUST_STANDBY 3 /* CoreStandby Mode */
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static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
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static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
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{
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{
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@ -59,7 +65,7 @@ static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
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int k;
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int k;
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for (k = 0; k < 1000; k++) {
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for (k = 0; k < 1000; k++) {
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if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3)
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if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
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return 1;
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return 1;
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mdelay(1);
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mdelay(1);
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