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[IA64] correct some messages and fixes some minor things
This patch corrects some wrong comments and a printk message. It also fixes some minor things, and makes all lines fit in 80 columns. Signed-off-by: Satoru Takeuchi <takeuchi_satoru@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Satoru Takeuchi
Tony Luck
parent
769ebc66de
commit
46cba3dcae
@ -9,54 +9,65 @@
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* Copyright (C) 1999 VA Linux Systems
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* Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
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*
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* 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
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* In particular, we now have separate handlers for edge
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* and level triggered interrupts.
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* 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
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* PCI to vector mapping, shared PCI interrupts.
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* 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
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* Clean up much of the old IOSAPIC cruft.
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* 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for
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* ACPI S5(SoftOff) support.
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* 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
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* APIC code. In particular, we now have separate
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* handlers for edge and level triggered
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* interrupts.
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* 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
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* allocation PCI to vector mapping, shared PCI
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* interrupts.
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* 00/10/27 D. Mosberger Document things a bit more to make them more
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* understandable. Clean up much of the old
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* IOSAPIC cruft.
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* 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
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* and fixes for ACPI S5(SoftOff) support.
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* 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
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* 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in
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* iosapic_set_affinity(), initializations for
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* /proc/irq/#/smp_affinity
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* 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
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* vectors in iosapic_set_affinity(),
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* initializations for /proc/irq/#/smp_affinity
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* 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
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* 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
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* 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
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* error
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* 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
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* IOSAPIC mapping error
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* 02/07/29 T. Kochi Allocate interrupt vectors dynamically
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* 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.)
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* 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code.
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* 02/08/04 T. Kochi Cleaned up terminology (irq, global system
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* interrupt, vector, etc.)
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* 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
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* pci_irq code.
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* 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
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* Remove iosapic_address & gsi_base from external interfaces.
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* Rationalize __init/__devinit attributes.
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* Remove iosapic_address & gsi_base from
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* external interfaces. Rationalize
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* __init/__devinit attributes.
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* 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
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* Updated to work with irq migration necessary for CPU Hotplug
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* Updated to work with irq migration necessary
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* for CPU Hotplug
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*/
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/*
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* Here is what the interrupt logic between a PCI device and the kernel looks like:
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* Here is what the interrupt logic between a PCI device and the kernel looks
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* like:
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*
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* (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
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* device is uniquely identified by its bus--, and slot-number (the function
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* number does not matter here because all functions share the same interrupt
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* lines).
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* (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
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* INTD). The device is uniquely identified by its bus-, and slot-number
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* (the function number does not matter here because all functions share
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* the same interrupt lines).
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*
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* (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
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* Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
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* triggered and use the same polarity). Each interrupt line has a unique Global
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* System Interrupt (GSI) number which can be calculated as the sum of the controller's
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* base GSI number and the IOSAPIC pin number to which the line connects.
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* (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
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* controller. Multiple interrupt lines may have to share the same
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* IOSAPIC pin (if they're level triggered and use the same polarity).
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* Each interrupt line has a unique Global System Interrupt (GSI) number
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* which can be calculated as the sum of the controller's base GSI number
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* and the IOSAPIC pin number to which the line connects.
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*
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* (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
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* into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU.
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* (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
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* IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
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* sent to the CPU.
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*
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* (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as
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* architecture-independent interrupt handling mechanism in Linux. As an
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* IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
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* mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and
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* IRQ. A platform can implement platform_irq_to_vector(irq) and
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* (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
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* used as architecture-independent interrupt handling mechanism in Linux.
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* As an IRQ is a number, we have to have
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* IA-64 interrupt vector number <-> IRQ number mapping. On smaller
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* systems, we use one-to-one mapping between IA-64 vector and IRQ. A
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* platform can implement platform_irq_to_vector(irq) and
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* platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
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* Please see also include/asm-ia64/hw_irq.h for those APIs.
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*
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@ -64,9 +75,9 @@
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*
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* PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
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*
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* Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
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* Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this
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* source code.
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* Note: The term "IRQ" is loosely used everywhere in Linux kernel to
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* describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
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* (isa_irq) is the only exception in this source code.
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*/
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#include <linux/config.h>
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@ -90,7 +101,6 @@
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#undef DEBUG_INTERRUPT_ROUTING
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#ifdef DEBUG_INTERRUPT_ROUTING
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@ -99,36 +109,46 @@
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#define DBG(fmt...)
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#endif
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#define NR_PREALLOCATE_RTE_ENTRIES (PAGE_SIZE / sizeof(struct iosapic_rte_info))
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#define NR_PREALLOCATE_RTE_ENTRIES \
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(PAGE_SIZE / sizeof(struct iosapic_rte_info))
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#define RTE_PREALLOCATED (1)
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static DEFINE_SPINLOCK(iosapic_lock);
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/* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
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/*
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* These tables map IA-64 vectors to the IOSAPIC pin that generates this
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* vector.
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*/
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struct iosapic_rte_info {
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struct list_head rte_list; /* node in list of RTEs sharing the same vector */
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struct list_head rte_list; /* node in list of RTEs sharing the
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* same vector */
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char __iomem *addr; /* base address of IOSAPIC */
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unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
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unsigned int gsi_base; /* first GSI assigned to this
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* IOSAPIC */
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char rte_index; /* IOSAPIC RTE index */
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int refcnt; /* reference counter */
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unsigned int flags; /* flags */
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} ____cacheline_aligned;
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static struct iosapic_intr_info {
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struct list_head rtes; /* RTEs using this vector (empty => not an IOSAPIC interrupt) */
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struct list_head rtes; /* RTEs using this vector (empty =>
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* not an IOSAPIC interrupt) */
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int count; /* # of RTEs that shares this vector */
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u32 low32; /* current value of low word of Redirection table entry */
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u32 low32; /* current value of low word of
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* Redirection table entry */
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unsigned int dest; /* destination CPU physical ID */
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unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
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unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */
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unsigned char polarity: 1; /* interrupt polarity
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* (see iosapic.h) */
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unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
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} iosapic_intr_info[IA64_NUM_VECTORS];
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static struct iosapic {
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char __iomem *addr; /* base address of IOSAPIC */
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unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
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unsigned short num_rte; /* number of RTE in this IOSAPIC */
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unsigned int gsi_base; /* first GSI assigned to this
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* IOSAPIC */
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unsigned short num_rte; /* # of RTEs on this IOSAPIC */
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int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
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#ifdef CONFIG_NUMA
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unsigned short node; /* numa node association via pxm */
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@ -149,7 +169,8 @@ find_iosapic (unsigned int gsi)
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int i;
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for (i = 0; i < NR_IOSAPICS; i++) {
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if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
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if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
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iosapic_lists[i].num_rte)
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return i;
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}
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@ -162,7 +183,8 @@ _gsi_to_vector (unsigned int gsi)
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struct iosapic_intr_info *info;
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struct iosapic_rte_info *rte;
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for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
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for (info = iosapic_intr_info; info <
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iosapic_intr_info + IA64_NUM_VECTORS; ++info)
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list_for_each_entry(rte, &info->rtes, rte_list)
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if (rte->gsi_base + rte->rte_index == gsi)
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return info - iosapic_intr_info;
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@ -185,8 +207,8 @@ gsi_to_irq (unsigned int gsi)
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unsigned long flags;
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int irq;
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/*
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* XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
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* numbers...
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* XXX fix me: this assumes an identity mapping between IA-64 vector
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* and Linux irq numbers...
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*/
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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@ -197,7 +219,8 @@ gsi_to_irq (unsigned int gsi)
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return irq;
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}
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static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi, unsigned int vec)
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static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi,
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unsigned int vec)
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{
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struct iosapic_rte_info *rte;
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@ -237,7 +260,9 @@ set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
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for (irq = 0; irq < NR_IRQS; ++irq)
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if (irq_to_vector(irq) == vector) {
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set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
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set_irq_affinity_info(irq,
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(int)(dest & 0xffff),
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redir);
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break;
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}
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}
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@ -259,7 +284,7 @@ set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
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}
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static void
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nop (unsigned int vector)
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nop (unsigned int irq)
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{
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/* do nothing... */
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}
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@ -281,7 +306,8 @@ mask_irq (unsigned int irq)
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{
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/* set only the mask bit */
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low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
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rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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@ -306,7 +332,8 @@ unmask_irq (unsigned int irq)
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
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rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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@ -346,21 +373,25 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
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spin_lock_irqsave(&iosapic_lock, flags);
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{
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low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
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low32 = iosapic_intr_info[vec].low32 &
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~(7 << IOSAPIC_DELIVERY_SHIFT);
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if (redir)
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/* change delivery mode to lowest priority */
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low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
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low32 |= (IOSAPIC_LOWEST_PRIORITY <<
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IOSAPIC_DELIVERY_SHIFT);
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else
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/* change delivery mode to fixed */
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low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
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iosapic_intr_info[vec].low32 = low32;
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iosapic_intr_info[vec].dest = dest;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
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rte_list) {
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addr = rte->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
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iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index),
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high32);
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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}
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@ -433,7 +464,8 @@ iosapic_ack_edge_irq (unsigned int irq)
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* interrupt for real. This prevents IRQ storms from unhandled
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* devices.
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*/
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if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
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if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
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(IRQ_PENDING|IRQ_DISABLED))
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mask_irq(irq);
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}
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@ -467,7 +499,8 @@ iosapic_version (char __iomem *addr)
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return iosapic_read(addr, IOSAPIC_VERSION);
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}
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static int iosapic_find_sharable_vector (unsigned long trigger, unsigned long pol)
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static int iosapic_find_sharable_vector (unsigned long trigger,
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unsigned long pol)
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{
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int i, vector = -1, min_count = -1;
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struct iosapic_intr_info *info;
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@ -482,7 +515,8 @@ static int iosapic_find_sharable_vector (unsigned long trigger, unsigned long po
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for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) {
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info = &iosapic_intr_info[i];
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if (info->trigger == trigger && info->polarity == pol &&
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(info->dmode == IOSAPIC_FIXED || info->dmode == IOSAPIC_LOWEST_PRIORITY)) {
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(info->dmode == IOSAPIC_FIXED || info->dmode ==
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IOSAPIC_LOWEST_PRIORITY)) {
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if (min_count == -1 || info->count < min_count) {
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vector = i;
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min_count = info->count;
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@ -506,12 +540,15 @@ iosapic_reassign_vector (int vector)
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new_vector = assign_irq_vector(AUTO_ASSIGN);
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if (new_vector < 0)
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panic("%s: out of interrupt vectors!\n", __FUNCTION__);
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printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector);
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printk(KERN_INFO "Reassigning vector %d to %d\n",
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vector, new_vector);
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memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
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sizeof(struct iosapic_intr_info));
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INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes);
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list_move(iosapic_intr_info[vector].rtes.next, &iosapic_intr_info[new_vector].rtes);
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memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
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list_move(iosapic_intr_info[vector].rtes.next,
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&iosapic_intr_info[new_vector].rtes);
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memset(&iosapic_intr_info[vector], 0,
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sizeof(struct iosapic_intr_info));
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iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
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INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
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}
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@ -524,7 +561,8 @@ static struct iosapic_rte_info *iosapic_alloc_rte (void)
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int preallocated = 0;
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if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
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rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * NR_PREALLOCATE_RTE_ENTRIES);
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rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
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NR_PREALLOCATE_RTE_ENTRIES);
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if (!rte)
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return NULL;
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for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
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@ -532,7 +570,8 @@ static struct iosapic_rte_info *iosapic_alloc_rte (void)
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}
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if (!list_empty(&free_rte_list)) {
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rte = list_entry(free_rte_list.next, struct iosapic_rte_info, rte_list);
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rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
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rte_list);
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list_del(&rte->rte_list);
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preallocated++;
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} else {
|
||||
@ -575,7 +614,8 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
|
||||
|
||||
index = find_iosapic(gsi);
|
||||
if (index < 0) {
|
||||
printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", __FUNCTION__, gsi);
|
||||
printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
|
||||
__FUNCTION__, gsi);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
@ -586,7 +626,8 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
|
||||
if (!rte) {
|
||||
rte = iosapic_alloc_rte();
|
||||
if (!rte) {
|
||||
printk(KERN_WARNING "%s: cannot allocate memory\n", __FUNCTION__);
|
||||
printk(KERN_WARNING "%s: cannot allocate memory\n",
|
||||
__FUNCTION__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
@ -602,7 +643,9 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
|
||||
else if (vector_is_shared(vector)) {
|
||||
struct iosapic_intr_info *info = &iosapic_intr_info[vector];
|
||||
if (info->trigger != trigger || info->polarity != polarity) {
|
||||
printk (KERN_WARNING "%s: cannot override the interrupt\n", __FUNCTION__);
|
||||
printk (KERN_WARNING
|
||||
"%s: cannot override the interrupt\n",
|
||||
__FUNCTION__);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
@ -619,8 +662,10 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
|
||||
idesc = irq_descp(vector);
|
||||
if (idesc->handler != irq_type) {
|
||||
if (idesc->handler != &no_irq_type)
|
||||
printk(KERN_WARNING "%s: changing vector %d from %s to %s\n",
|
||||
__FUNCTION__, vector, idesc->handler->typename, irq_type->typename);
|
||||
printk(KERN_WARNING
|
||||
"%s: changing vector %d from %s to %s\n",
|
||||
__FUNCTION__, vector,
|
||||
idesc->handler->typename, irq_type->typename);
|
||||
idesc->handler = irq_type;
|
||||
}
|
||||
return 0;
|
||||
@ -681,7 +726,7 @@ get_target_cpu (unsigned int gsi, int vector)
|
||||
if (!num_cpus)
|
||||
goto skip_numa_setup;
|
||||
|
||||
/* Use vector assigment to distribute across cpus in node */
|
||||
/* Use vector assignment to distribute across cpus in node */
|
||||
cpu_index = vector % num_cpus;
|
||||
|
||||
for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
|
||||
@ -703,7 +748,7 @@ skip_numa_setup:
|
||||
} while (!cpu_online(cpu));
|
||||
|
||||
return cpu_physical_id(cpu);
|
||||
#else
|
||||
#else /* CONFIG_SMP */
|
||||
return cpu_physical_id(smp_processor_id());
|
||||
#endif
|
||||
}
|
||||
@ -755,7 +800,8 @@ again:
|
||||
if (list_empty(&iosapic_intr_info[vector].rtes))
|
||||
free_irq_vector(vector);
|
||||
spin_unlock(&iosapic_lock);
|
||||
spin_unlock_irqrestore(&irq_descp(vector)->lock, flags);
|
||||
spin_unlock_irqrestore(&irq_descp(vector)->lock,
|
||||
flags);
|
||||
goto again;
|
||||
}
|
||||
|
||||
@ -764,7 +810,8 @@ again:
|
||||
polarity, trigger);
|
||||
if (err < 0) {
|
||||
spin_unlock(&iosapic_lock);
|
||||
spin_unlock_irqrestore(&irq_descp(vector)->lock, flags);
|
||||
spin_unlock_irqrestore(&irq_descp(vector)->lock,
|
||||
flags);
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -806,7 +853,8 @@ iosapic_unregister_intr (unsigned int gsi)
|
||||
*/
|
||||
irq = gsi_to_irq(gsi);
|
||||
if (irq < 0) {
|
||||
printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi);
|
||||
printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
|
||||
gsi);
|
||||
WARN_ON(1);
|
||||
return;
|
||||
}
|
||||
@ -817,7 +865,9 @@ iosapic_unregister_intr (unsigned int gsi)
|
||||
spin_lock(&iosapic_lock);
|
||||
{
|
||||
if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
|
||||
printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi);
|
||||
printk(KERN_ERR
|
||||
"iosapic_unregister_intr(%u) unbalanced\n",
|
||||
gsi);
|
||||
WARN_ON(1);
|
||||
goto out;
|
||||
}
|
||||
@ -827,7 +877,8 @@ iosapic_unregister_intr (unsigned int gsi)
|
||||
|
||||
/* Mask the interrupt */
|
||||
low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
|
||||
iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32);
|
||||
iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index),
|
||||
low32);
|
||||
|
||||
/* Remove the rte entry from the list */
|
||||
list_del(&rte->rte_list);
|
||||
@ -840,7 +891,9 @@ iosapic_unregister_intr (unsigned int gsi)
|
||||
trigger = iosapic_intr_info[vector].trigger;
|
||||
polarity = iosapic_intr_info[vector].polarity;
|
||||
dest = iosapic_intr_info[vector].dest;
|
||||
printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
|
||||
printk(KERN_INFO
|
||||
"GSI %u (%s, %s) -> CPU %d (0x%04x)"
|
||||
" vector %d unregistered\n",
|
||||
gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
|
||||
(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
|
||||
cpu_logical_id(dest), dest, vector);
|
||||
@ -853,12 +906,15 @@ iosapic_unregister_intr (unsigned int gsi)
|
||||
idesc->handler = &no_irq_type;
|
||||
|
||||
/* Clear the interrupt information */
|
||||
memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
|
||||
memset(&iosapic_intr_info[vector], 0,
|
||||
sizeof(struct iosapic_intr_info));
|
||||
iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
|
||||
INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
|
||||
|
||||
if (idesc->action) {
|
||||
printk(KERN_ERR "interrupt handlers still exist on IRQ %u\n", irq);
|
||||
printk(KERN_ERR
|
||||
"interrupt handlers still exist on"
|
||||
"IRQ %u\n", irq);
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
@ -873,7 +929,6 @@ iosapic_unregister_intr (unsigned int gsi)
|
||||
|
||||
/*
|
||||
* ACPI calls this when it finds an entry for a platform interrupt.
|
||||
* Note that the irq_base and IOSAPIC address must be set in iosapic_init().
|
||||
*/
|
||||
int __init
|
||||
iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
|
||||
@ -907,13 +962,16 @@ iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
|
||||
mask = 1;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type);
|
||||
printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
|
||||
int_type);
|
||||
return -1;
|
||||
}
|
||||
|
||||
register_intr(gsi, vector, delivery, polarity, trigger);
|
||||
|
||||
printk(KERN_INFO "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
|
||||
printk(KERN_INFO
|
||||
"PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
|
||||
" vector %d\n",
|
||||
int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
|
||||
int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
|
||||
(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
|
||||
@ -923,10 +981,8 @@ iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
|
||||
return vector;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* ACPI calls this when it finds an entry for a legacy ISA IRQ override.
|
||||
* Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
|
||||
*/
|
||||
void __init
|
||||
iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
|
||||
@ -955,16 +1011,19 @@ iosapic_system_init (int system_pcat_compat)
|
||||
|
||||
for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) {
|
||||
iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
|
||||
INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); /* mark as unused */
|
||||
/* mark as unused */
|
||||
INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
|
||||
}
|
||||
|
||||
pcat_compat = system_pcat_compat;
|
||||
if (pcat_compat) {
|
||||
/*
|
||||
* Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
|
||||
* enabled.
|
||||
* Disable the compatibility mode interrupts (8259 style),
|
||||
* needs IN/OUT support enabled.
|
||||
*/
|
||||
printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
|
||||
printk(KERN_INFO
|
||||
"%s: Disabling PC-AT compatible 8259 interrupts\n",
|
||||
__FUNCTION__);
|
||||
outb(0xff, 0xA1);
|
||||
outb(0xff, 0x21);
|
||||
}
|
||||
@ -1053,12 +1112,14 @@ iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
|
||||
|
||||
if ((gsi_base == 0) && pcat_compat) {
|
||||
/*
|
||||
* Map the legacy ISA devices into the IOSAPIC data. Some of these may
|
||||
* get reprogrammed later on with data from the ACPI Interrupt Source
|
||||
* Override table.
|
||||
* Map the legacy ISA devices into the IOSAPIC data. Some of
|
||||
* these may get reprogrammed later on with data from the ACPI
|
||||
* Interrupt Source Override table.
|
||||
*/
|
||||
for (isa_irq = 0; isa_irq < 16; ++isa_irq)
|
||||
iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE);
|
||||
iosapic_override_isa_irq(isa_irq, isa_irq,
|
||||
IOSAPIC_POL_HIGH,
|
||||
IOSAPIC_EDGE);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -1081,7 +1142,8 @@ iosapic_remove (unsigned int gsi_base)
|
||||
|
||||
if (iosapic_lists[index].rtes_inuse) {
|
||||
err = -EBUSY;
|
||||
printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
|
||||
printk(KERN_WARNING
|
||||
"%s: IOSAPIC for GSI base %u is busy\n",
|
||||
__FUNCTION__, gsi_base);
|
||||
goto out;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user