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cxgb4: add iSCSI DDP page pod manager
add files for common page pod manager, both iSCSI initiator and target ULDs will use common ppod manager for DDP. Signed-off-by: Varun Prakash <varun@chelsio.com> Acked-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: Nicholas Bellinger <nab@linux-iscsi.org>
This commit is contained in:
Varun Prakash
Nicholas Bellinger
parent
cb6a8ff070
commit
47da7e62b3
464
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.c
Normal file
464
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.c
Normal file
@ -0,0 +1,464 @@
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/*
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* cxgb4_ppm.c: Chelsio common library for T4/T5 iSCSI PagePod Manager
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*
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* Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Written by: Karen Xie (kxie@chelsio.com)
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*/
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#include <linux/kernel.h>
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/debugfs.h>
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#include <linux/export.h>
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#include <linux/list.h>
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#include <linux/skbuff.h>
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#include <linux/pci.h>
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#include <linux/scatterlist.h>
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#include "cxgb4_ppm.h"
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/* Direct Data Placement -
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* Directly place the iSCSI Data-In or Data-Out PDU's payload into
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* pre-posted final destination host-memory buffers based on the
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* Initiator Task Tag (ITT) in Data-In or Target Task Tag (TTT)
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* in Data-Out PDUs. The host memory address is programmed into
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* h/w in the format of pagepod entries. The location of the
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* pagepod entry is encoded into ddp tag which is used as the base
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* for ITT/TTT.
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*/
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/* Direct-Data Placement page size adjustment
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*/
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int cxgbi_ppm_find_page_index(struct cxgbi_ppm *ppm, unsigned long pgsz)
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{
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struct cxgbi_tag_format *tformat = &ppm->tformat;
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int i;
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for (i = 0; i < DDP_PGIDX_MAX; i++) {
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if (pgsz == 1UL << (DDP_PGSZ_BASE_SHIFT +
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tformat->pgsz_order[i])) {
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pr_debug("%s: %s ppm, pgsz %lu -> idx %d.\n",
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__func__, ppm->ndev->name, pgsz, i);
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return i;
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}
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}
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pr_info("ippm: ddp page size %lu not supported.\n", pgsz);
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return DDP_PGIDX_MAX;
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}
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/* DDP setup & teardown
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*/
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static int ppm_find_unused_entries(unsigned long *bmap,
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unsigned int max_ppods,
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unsigned int start,
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unsigned int nr,
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unsigned int align_mask)
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{
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unsigned long i;
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i = bitmap_find_next_zero_area(bmap, max_ppods, start, nr, align_mask);
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if (unlikely(i >= max_ppods) && (start > nr))
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i = bitmap_find_next_zero_area(bmap, max_ppods, 0, start - 1,
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align_mask);
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if (unlikely(i >= max_ppods))
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return -ENOSPC;
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bitmap_set(bmap, i, nr);
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return (int)i;
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}
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static void ppm_mark_entries(struct cxgbi_ppm *ppm, int i, int count,
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unsigned long caller_data)
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{
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struct cxgbi_ppod_data *pdata = ppm->ppod_data + i;
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pdata->caller_data = caller_data;
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pdata->npods = count;
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if (pdata->color == ((1 << PPOD_IDX_SHIFT) - 1))
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pdata->color = 0;
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else
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pdata->color++;
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}
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static int ppm_get_cpu_entries(struct cxgbi_ppm *ppm, unsigned int count,
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unsigned long caller_data)
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{
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struct cxgbi_ppm_pool *pool;
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unsigned int cpu;
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int i;
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cpu = get_cpu();
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pool = per_cpu_ptr(ppm->pool, cpu);
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spin_lock_bh(&pool->lock);
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put_cpu();
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i = ppm_find_unused_entries(pool->bmap, ppm->pool_index_max,
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pool->next, count, 0);
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if (i < 0) {
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pool->next = 0;
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spin_unlock_bh(&pool->lock);
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return -ENOSPC;
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}
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pool->next = i + count;
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if (pool->next >= ppm->pool_index_max)
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pool->next = 0;
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spin_unlock_bh(&pool->lock);
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pr_debug("%s: cpu %u, idx %d + %d (%d), next %u.\n",
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__func__, cpu, i, count, i + cpu * ppm->pool_index_max,
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pool->next);
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i += cpu * ppm->pool_index_max;
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ppm_mark_entries(ppm, i, count, caller_data);
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return i;
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}
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static int ppm_get_entries(struct cxgbi_ppm *ppm, unsigned int count,
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unsigned long caller_data)
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{
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int i;
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spin_lock_bh(&ppm->map_lock);
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i = ppm_find_unused_entries(ppm->ppod_bmap, ppm->bmap_index_max,
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ppm->next, count, 0);
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if (i < 0) {
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ppm->next = 0;
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spin_unlock_bh(&ppm->map_lock);
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pr_debug("ippm: NO suitable entries %u available.\n",
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count);
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return -ENOSPC;
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}
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ppm->next = i + count;
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if (ppm->next >= ppm->bmap_index_max)
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ppm->next = 0;
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spin_unlock_bh(&ppm->map_lock);
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pr_debug("%s: idx %d + %d (%d), next %u, caller_data 0x%lx.\n",
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__func__, i, count, i + ppm->pool_rsvd, ppm->next,
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caller_data);
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i += ppm->pool_rsvd;
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ppm_mark_entries(ppm, i, count, caller_data);
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return i;
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}
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static void ppm_unmark_entries(struct cxgbi_ppm *ppm, int i, int count)
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{
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pr_debug("%s: idx %d + %d.\n", __func__, i, count);
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if (i < ppm->pool_rsvd) {
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unsigned int cpu;
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struct cxgbi_ppm_pool *pool;
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cpu = i / ppm->pool_index_max;
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i %= ppm->pool_index_max;
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pool = per_cpu_ptr(ppm->pool, cpu);
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spin_lock_bh(&pool->lock);
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bitmap_clear(pool->bmap, i, count);
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if (i < pool->next)
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pool->next = i;
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spin_unlock_bh(&pool->lock);
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pr_debug("%s: cpu %u, idx %d, next %u.\n",
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__func__, cpu, i, pool->next);
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} else {
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spin_lock_bh(&ppm->map_lock);
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i -= ppm->pool_rsvd;
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bitmap_clear(ppm->ppod_bmap, i, count);
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if (i < ppm->next)
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ppm->next = i;
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spin_unlock_bh(&ppm->map_lock);
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pr_debug("%s: idx %d, next %u.\n", __func__, i, ppm->next);
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}
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}
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void cxgbi_ppm_ppod_release(struct cxgbi_ppm *ppm, u32 idx)
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{
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struct cxgbi_ppod_data *pdata;
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if (idx >= ppm->ppmax) {
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pr_warn("ippm: idx too big %u > %u.\n", idx, ppm->ppmax);
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return;
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}
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pdata = ppm->ppod_data + idx;
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if (!pdata->npods) {
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pr_warn("ippm: idx %u, npods 0.\n", idx);
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return;
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}
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pr_debug("release idx %u, npods %u.\n", idx, pdata->npods);
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ppm_unmark_entries(ppm, idx, pdata->npods);
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}
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EXPORT_SYMBOL(cxgbi_ppm_ppod_release);
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int cxgbi_ppm_ppods_reserve(struct cxgbi_ppm *ppm, unsigned short nr_pages,
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u32 per_tag_pg_idx, u32 *ppod_idx,
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u32 *ddp_tag, unsigned long caller_data)
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{
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struct cxgbi_ppod_data *pdata;
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unsigned int npods;
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int idx = -1;
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unsigned int hwidx;
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u32 tag;
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npods = (nr_pages + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT;
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if (!npods) {
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pr_warn("%s: pages %u -> npods %u, full.\n",
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__func__, nr_pages, npods);
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return -EINVAL;
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}
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/* grab from cpu pool first */
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idx = ppm_get_cpu_entries(ppm, npods, caller_data);
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/* try the general pool */
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if (idx < 0)
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idx = ppm_get_entries(ppm, npods, caller_data);
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if (idx < 0) {
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pr_debug("ippm: pages %u, nospc %u, nxt %u, 0x%lx.\n",
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nr_pages, npods, ppm->next, caller_data);
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return idx;
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}
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pdata = ppm->ppod_data + idx;
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hwidx = ppm->base_idx + idx;
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tag = cxgbi_ppm_make_ddp_tag(hwidx, pdata->color);
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if (per_tag_pg_idx)
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tag |= (per_tag_pg_idx << 30) & 0xC0000000;
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*ppod_idx = idx;
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*ddp_tag = tag;
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pr_debug("ippm: sg %u, tag 0x%x(%u,%u), data 0x%lx.\n",
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nr_pages, tag, idx, npods, caller_data);
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return npods;
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}
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EXPORT_SYMBOL(cxgbi_ppm_ppods_reserve);
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void cxgbi_ppm_make_ppod_hdr(struct cxgbi_ppm *ppm, u32 tag,
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unsigned int tid, unsigned int offset,
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unsigned int length,
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struct cxgbi_pagepod_hdr *hdr)
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{
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/* The ddp tag in pagepod should be with bit 31:30 set to 0.
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* The ddp Tag on the wire should be with non-zero 31:30 to the peer
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*/
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tag &= 0x3FFFFFFF;
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hdr->vld_tid = htonl(PPOD_VALID_FLAG | PPOD_TID(tid));
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hdr->rsvd = 0;
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hdr->pgsz_tag_clr = htonl(tag & ppm->tformat.idx_clr_mask);
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hdr->max_offset = htonl(length);
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hdr->page_offset = htonl(offset);
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pr_debug("ippm: tag 0x%x, tid 0x%x, xfer %u, off %u.\n",
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tag, tid, length, offset);
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}
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EXPORT_SYMBOL(cxgbi_ppm_make_ppod_hdr);
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static void ppm_free(struct cxgbi_ppm *ppm)
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{
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vfree(ppm);
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}
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static void ppm_destroy(struct kref *kref)
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{
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struct cxgbi_ppm *ppm = container_of(kref,
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struct cxgbi_ppm,
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refcnt);
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pr_info("ippm: kref 0, destroy %s ppm 0x%p.\n",
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ppm->ndev->name, ppm);
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*ppm->ppm_pp = NULL;
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free_percpu(ppm->pool);
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ppm_free(ppm);
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}
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int cxgbi_ppm_release(struct cxgbi_ppm *ppm)
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{
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if (ppm) {
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int rv;
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rv = kref_put(&ppm->refcnt, ppm_destroy);
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return rv;
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}
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return 1;
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}
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static struct cxgbi_ppm_pool *ppm_alloc_cpu_pool(unsigned int *total,
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unsigned int *pcpu_ppmax)
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{
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struct cxgbi_ppm_pool *pools;
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unsigned int ppmax = (*total) / num_possible_cpus();
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unsigned int max = (PCPU_MIN_UNIT_SIZE - sizeof(*pools)) << 3;
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unsigned int bmap;
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unsigned int alloc_sz;
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unsigned int count = 0;
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unsigned int cpu;
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/* make sure per cpu pool fits into PCPU_MIN_UNIT_SIZE */
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if (ppmax > max)
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ppmax = max;
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/* pool size must be multiple of unsigned long */
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bmap = BITS_TO_LONGS(ppmax);
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ppmax = (bmap * sizeof(unsigned long)) << 3;
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alloc_sz = sizeof(*pools) + sizeof(unsigned long) * bmap;
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pools = __alloc_percpu(alloc_sz, __alignof__(struct cxgbi_ppm_pool));
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if (!pools)
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return NULL;
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for_each_possible_cpu(cpu) {
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struct cxgbi_ppm_pool *ppool = per_cpu_ptr(pools, cpu);
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memset(ppool, 0, alloc_sz);
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spin_lock_init(&ppool->lock);
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count += ppmax;
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}
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*total = count;
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*pcpu_ppmax = ppmax;
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return pools;
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}
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int cxgbi_ppm_init(void **ppm_pp, struct net_device *ndev,
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struct pci_dev *pdev, void *lldev,
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struct cxgbi_tag_format *tformat,
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unsigned int ppmax,
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unsigned int llimit,
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unsigned int start,
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unsigned int reserve_factor)
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{
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struct cxgbi_ppm *ppm = (struct cxgbi_ppm *)(*ppm_pp);
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struct cxgbi_ppm_pool *pool = NULL;
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unsigned int ppmax_pool = 0;
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unsigned int pool_index_max = 0;
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unsigned int alloc_sz;
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unsigned int ppod_bmap_size;
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if (ppm) {
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pr_info("ippm: %s, ppm 0x%p,0x%p already initialized, %u/%u.\n",
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ndev->name, ppm_pp, ppm, ppm->ppmax, ppmax);
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kref_get(&ppm->refcnt);
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return 1;
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}
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if (reserve_factor) {
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ppmax_pool = ppmax / reserve_factor;
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pool = ppm_alloc_cpu_pool(&ppmax_pool, &pool_index_max);
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pr_debug("%s: ppmax %u, cpu total %u, per cpu %u.\n",
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ndev->name, ppmax, ppmax_pool, pool_index_max);
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}
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ppod_bmap_size = BITS_TO_LONGS(ppmax - ppmax_pool);
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alloc_sz = sizeof(struct cxgbi_ppm) +
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ppmax * (sizeof(struct cxgbi_ppod_data)) +
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ppod_bmap_size * sizeof(unsigned long);
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ppm = vmalloc(alloc_sz);
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if (!ppm)
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goto release_ppm_pool;
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memset(ppm, 0, alloc_sz);
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ppm->ppod_bmap = (unsigned long *)(&ppm->ppod_data[ppmax]);
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if ((ppod_bmap_size >> 3) > (ppmax - ppmax_pool)) {
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unsigned int start = ppmax - ppmax_pool;
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unsigned int end = ppod_bmap_size >> 3;
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bitmap_set(ppm->ppod_bmap, ppmax, end - start);
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pr_info("%s: %u - %u < %u * 8, mask extra bits %u, %u.\n",
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__func__, ppmax, ppmax_pool, ppod_bmap_size, start,
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end);
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}
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spin_lock_init(&ppm->map_lock);
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kref_init(&ppm->refcnt);
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memcpy(&ppm->tformat, tformat, sizeof(struct cxgbi_tag_format));
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ppm->ppm_pp = ppm_pp;
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ppm->ndev = ndev;
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ppm->pdev = pdev;
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ppm->lldev = lldev;
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ppm->ppmax = ppmax;
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ppm->next = 0;
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ppm->llimit = llimit;
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ppm->base_idx = start > llimit ?
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(start - llimit + 1) >> PPOD_SIZE_SHIFT : 0;
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ppm->bmap_index_max = ppmax - ppmax_pool;
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ppm->pool = pool;
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ppm->pool_rsvd = ppmax_pool;
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ppm->pool_index_max = pool_index_max;
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/* check one more time */
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if (*ppm_pp) {
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ppm_free(ppm);
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ppm = (struct cxgbi_ppm *)(*ppm_pp);
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pr_info("ippm: %s, ppm 0x%p,0x%p already initialized, %u/%u.\n",
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ndev->name, ppm_pp, *ppm_pp, ppm->ppmax, ppmax);
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kref_get(&ppm->refcnt);
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return 1;
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}
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*ppm_pp = ppm;
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ppm->tformat.pgsz_idx_dflt = cxgbi_ppm_find_page_index(ppm, PAGE_SIZE);
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pr_info("ippm %s: ppm 0x%p, 0x%p, base %u/%u, pg %lu,%u, rsvd %u,%u.\n",
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ndev->name, ppm_pp, ppm, ppm->base_idx, ppm->ppmax, PAGE_SIZE,
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ppm->tformat.pgsz_idx_dflt, ppm->pool_rsvd,
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ppm->pool_index_max);
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return 0;
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release_ppm_pool:
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free_percpu(pool);
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return -ENOMEM;
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}
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EXPORT_SYMBOL(cxgbi_ppm_init);
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unsigned int cxgbi_tagmask_set(unsigned int ppmax)
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{
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unsigned int bits = fls(ppmax);
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if (bits > PPOD_IDX_MAX_SIZE)
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bits = PPOD_IDX_MAX_SIZE;
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||||
|
||||
pr_info("ippm: ppmax %u/0x%x -> bits %u, tagmask 0x%x.\n",
|
||||
ppmax, ppmax, bits, 1 << (bits + PPOD_IDX_SHIFT));
|
||||
|
||||
return 1 << (bits + PPOD_IDX_SHIFT);
|
||||
}
|
||||
310
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.h
Normal file
310
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.h
Normal file
@ -0,0 +1,310 @@
|
||||
/*
|
||||
* cxgb4_ppm.h: Chelsio common library for T4/T5 iSCSI ddp operation
|
||||
*
|
||||
* Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Written by: Karen Xie (kxie@chelsio.com)
|
||||
*/
|
||||
|
||||
#ifndef __CXGB4PPM_H__
|
||||
#define __CXGB4PPM_H__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/bitmap.h>
|
||||
|
||||
struct cxgbi_pagepod_hdr {
|
||||
u32 vld_tid;
|
||||
u32 pgsz_tag_clr;
|
||||
u32 max_offset;
|
||||
u32 page_offset;
|
||||
u64 rsvd;
|
||||
};
|
||||
|
||||
#define PPOD_PAGES_MAX 4
|
||||
struct cxgbi_pagepod {
|
||||
struct cxgbi_pagepod_hdr hdr;
|
||||
u64 addr[PPOD_PAGES_MAX + 1];
|
||||
};
|
||||
|
||||
/* ddp tag format
|
||||
* for a 32-bit tag:
|
||||
* bit #
|
||||
* 31 ..... ..... 0
|
||||
* X Y...Y Z...Z, where
|
||||
* ^ ^^^^^ ^^^^
|
||||
* | | |____ when ddp bit = 0: color bits
|
||||
* | |
|
||||
* | |____ when ddp bit = 0: idx into the ddp memory region
|
||||
* |
|
||||
* |____ ddp bit: 0 - ddp tag, 1 - non-ddp tag
|
||||
*
|
||||
* [page selector:2] [sw/free bits] [0] [idx] [color:6]
|
||||
*/
|
||||
|
||||
#define DDP_PGIDX_MAX 4
|
||||
#define DDP_PGSZ_BASE_SHIFT 12 /* base page 4K */
|
||||
|
||||
struct cxgbi_task_tag_info {
|
||||
unsigned char flags;
|
||||
#define CXGBI_PPOD_INFO_FLAG_VALID 0x1
|
||||
#define CXGBI_PPOD_INFO_FLAG_MAPPED 0x2
|
||||
unsigned char cid;
|
||||
unsigned short pg_shift;
|
||||
unsigned int npods;
|
||||
unsigned int idx;
|
||||
unsigned int tag;
|
||||
struct cxgbi_pagepod_hdr hdr;
|
||||
int nents;
|
||||
int nr_pages;
|
||||
struct scatterlist *sgl;
|
||||
};
|
||||
|
||||
struct cxgbi_tag_format {
|
||||
unsigned char pgsz_order[DDP_PGIDX_MAX];
|
||||
unsigned char pgsz_idx_dflt;
|
||||
unsigned char free_bits:4;
|
||||
unsigned char color_bits:4;
|
||||
unsigned char idx_bits;
|
||||
unsigned char rsvd_bits;
|
||||
unsigned int no_ddp_mask;
|
||||
unsigned int idx_mask;
|
||||
unsigned int color_mask;
|
||||
unsigned int idx_clr_mask;
|
||||
unsigned int rsvd_mask;
|
||||
};
|
||||
|
||||
struct cxgbi_ppod_data {
|
||||
unsigned char pg_idx:2;
|
||||
unsigned char color:6;
|
||||
unsigned char chan_id;
|
||||
unsigned short npods;
|
||||
unsigned long caller_data;
|
||||
};
|
||||
|
||||
/* per cpu ppm pool */
|
||||
struct cxgbi_ppm_pool {
|
||||
unsigned int base; /* base index */
|
||||
unsigned int next; /* next possible free index */
|
||||
spinlock_t lock; /* ppm pool lock */
|
||||
unsigned long bmap[0];
|
||||
} ____cacheline_aligned_in_smp;
|
||||
|
||||
struct cxgbi_ppm {
|
||||
struct kref refcnt;
|
||||
struct net_device *ndev; /* net_device, 1st port */
|
||||
struct pci_dev *pdev;
|
||||
void *lldev;
|
||||
void **ppm_pp;
|
||||
struct cxgbi_tag_format tformat;
|
||||
unsigned int ppmax;
|
||||
unsigned int llimit;
|
||||
unsigned int base_idx;
|
||||
|
||||
unsigned int pool_rsvd;
|
||||
unsigned int pool_index_max;
|
||||
struct cxgbi_ppm_pool __percpu *pool;
|
||||
/* map lock */
|
||||
spinlock_t map_lock; /* ppm map lock */
|
||||
unsigned int bmap_index_max;
|
||||
unsigned int next;
|
||||
unsigned long *ppod_bmap;
|
||||
struct cxgbi_ppod_data ppod_data[0];
|
||||
};
|
||||
|
||||
#define DDP_THRESHOLD 512
|
||||
|
||||
#define PPOD_PAGES_SHIFT 2 /* 4 pages per pod */
|
||||
|
||||
#define IPPOD_SIZE sizeof(struct cxgbi_pagepod) /* 64 */
|
||||
#define PPOD_SIZE_SHIFT 6
|
||||
|
||||
/* page pods are allocated in groups of this size (must be power of 2) */
|
||||
#define PPOD_CLUSTER_SIZE 16U
|
||||
|
||||
#define ULPMEM_DSGL_MAX_NPPODS 16 /* 1024/PPOD_SIZE */
|
||||
#define ULPMEM_IDATA_MAX_NPPODS 3 /* (PPOD_SIZE * 3 + ulptx hdr) < 256B */
|
||||
#define PCIE_MEMWIN_MAX_NPPODS 16 /* 1024/PPOD_SIZE */
|
||||
|
||||
#define PPOD_COLOR_SHIFT 0
|
||||
#define PPOD_COLOR(x) ((x) << PPOD_COLOR_SHIFT)
|
||||
|
||||
#define PPOD_IDX_SHIFT 6
|
||||
#define PPOD_IDX_MAX_SIZE 24
|
||||
|
||||
#define PPOD_TID_SHIFT 0
|
||||
#define PPOD_TID(x) ((x) << PPOD_TID_SHIFT)
|
||||
|
||||
#define PPOD_TAG_SHIFT 6
|
||||
#define PPOD_TAG(x) ((x) << PPOD_TAG_SHIFT)
|
||||
|
||||
#define PPOD_VALID_SHIFT 24
|
||||
#define PPOD_VALID(x) ((x) << PPOD_VALID_SHIFT)
|
||||
#define PPOD_VALID_FLAG PPOD_VALID(1U)
|
||||
|
||||
#define PPOD_PI_EXTRACT_CTL_SHIFT 31
|
||||
#define PPOD_PI_EXTRACT_CTL(x) ((x) << PPOD_PI_EXTRACT_CTL_SHIFT)
|
||||
#define PPOD_PI_EXTRACT_CTL_FLAG V_PPOD_PI_EXTRACT_CTL(1U)
|
||||
|
||||
#define PPOD_PI_TYPE_SHIFT 29
|
||||
#define PPOD_PI_TYPE_MASK 0x3
|
||||
#define PPOD_PI_TYPE(x) ((x) << PPOD_PI_TYPE_SHIFT)
|
||||
|
||||
#define PPOD_PI_CHECK_CTL_SHIFT 27
|
||||
#define PPOD_PI_CHECK_CTL_MASK 0x3
|
||||
#define PPOD_PI_CHECK_CTL(x) ((x) << PPOD_PI_CHECK_CTL_SHIFT)
|
||||
|
||||
#define PPOD_PI_REPORT_CTL_SHIFT 25
|
||||
#define PPOD_PI_REPORT_CTL_MASK 0x3
|
||||
#define PPOD_PI_REPORT_CTL(x) ((x) << PPOD_PI_REPORT_CTL_SHIFT)
|
||||
|
||||
static inline int cxgbi_ppm_is_ddp_tag(struct cxgbi_ppm *ppm, u32 tag)
|
||||
{
|
||||
return !(tag & ppm->tformat.no_ddp_mask);
|
||||
}
|
||||
|
||||
static inline int cxgbi_ppm_sw_tag_is_usable(struct cxgbi_ppm *ppm,
|
||||
u32 tag)
|
||||
{
|
||||
/* the sw tag must be using <= 31 bits */
|
||||
return !(tag & 0x80000000U);
|
||||
}
|
||||
|
||||
static inline int cxgbi_ppm_make_non_ddp_tag(struct cxgbi_ppm *ppm,
|
||||
u32 sw_tag,
|
||||
u32 *final_tag)
|
||||
{
|
||||
struct cxgbi_tag_format *tformat = &ppm->tformat;
|
||||
|
||||
if (!cxgbi_ppm_sw_tag_is_usable(ppm, sw_tag)) {
|
||||
pr_info("sw_tag 0x%x NOT usable.\n", sw_tag);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!sw_tag) {
|
||||
*final_tag = tformat->no_ddp_mask;
|
||||
} else {
|
||||
unsigned int shift = tformat->idx_bits + tformat->color_bits;
|
||||
u32 lower = sw_tag & tformat->idx_clr_mask;
|
||||
u32 upper = (sw_tag >> shift) << (shift + 1);
|
||||
|
||||
*final_tag = upper | tformat->no_ddp_mask | lower;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline u32 cxgbi_ppm_decode_non_ddp_tag(struct cxgbi_ppm *ppm,
|
||||
u32 tag)
|
||||
{
|
||||
struct cxgbi_tag_format *tformat = &ppm->tformat;
|
||||
unsigned int shift = tformat->idx_bits + tformat->color_bits;
|
||||
u32 lower = tag & tformat->idx_clr_mask;
|
||||
u32 upper = (tag >> tformat->rsvd_bits) << shift;
|
||||
|
||||
return upper | lower;
|
||||
}
|
||||
|
||||
static inline u32 cxgbi_ppm_ddp_tag_get_idx(struct cxgbi_ppm *ppm,
|
||||
u32 ddp_tag)
|
||||
{
|
||||
u32 hw_idx = (ddp_tag >> PPOD_IDX_SHIFT) &
|
||||
ppm->tformat.idx_mask;
|
||||
|
||||
return hw_idx - ppm->base_idx;
|
||||
}
|
||||
|
||||
static inline u32 cxgbi_ppm_make_ddp_tag(unsigned int hw_idx,
|
||||
unsigned char color)
|
||||
{
|
||||
return (hw_idx << PPOD_IDX_SHIFT) | ((u32)color);
|
||||
}
|
||||
|
||||
static inline unsigned long
|
||||
cxgbi_ppm_get_tag_caller_data(struct cxgbi_ppm *ppm,
|
||||
u32 ddp_tag)
|
||||
{
|
||||
u32 idx = cxgbi_ppm_ddp_tag_get_idx(ppm, ddp_tag);
|
||||
|
||||
return ppm->ppod_data[idx].caller_data;
|
||||
}
|
||||
|
||||
/* sw bits are the free bits */
|
||||
static inline int cxgbi_ppm_ddp_tag_update_sw_bits(struct cxgbi_ppm *ppm,
|
||||
u32 val, u32 orig_tag,
|
||||
u32 *final_tag)
|
||||
{
|
||||
struct cxgbi_tag_format *tformat = &ppm->tformat;
|
||||
u32 v = val >> tformat->free_bits;
|
||||
|
||||
if (v) {
|
||||
pr_info("sw_bits 0x%x too large, avail bits %u.\n",
|
||||
val, tformat->free_bits);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!cxgbi_ppm_is_ddp_tag(ppm, orig_tag))
|
||||
return -EINVAL;
|
||||
|
||||
*final_tag = (val << tformat->rsvd_bits) |
|
||||
(orig_tag & ppm->tformat.rsvd_mask);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void cxgbi_ppm_ppod_clear(struct cxgbi_pagepod *ppod)
|
||||
{
|
||||
ppod->hdr.vld_tid = 0U;
|
||||
}
|
||||
|
||||
static inline void cxgbi_tagmask_check(unsigned int tagmask,
|
||||
struct cxgbi_tag_format *tformat)
|
||||
{
|
||||
unsigned int bits = fls(tagmask);
|
||||
|
||||
/* reserve top most 2 bits for page selector */
|
||||
tformat->free_bits = 32 - 2 - bits;
|
||||
tformat->rsvd_bits = bits;
|
||||
tformat->color_bits = PPOD_IDX_SHIFT;
|
||||
tformat->idx_bits = bits - 1 - PPOD_IDX_SHIFT;
|
||||
tformat->no_ddp_mask = 1 << (bits - 1);
|
||||
tformat->idx_mask = (1 << tformat->idx_bits) - 1;
|
||||
tformat->color_mask = (1 << PPOD_IDX_SHIFT) - 1;
|
||||
tformat->idx_clr_mask = (1 << (bits - 1)) - 1;
|
||||
tformat->rsvd_mask = (1 << bits) - 1;
|
||||
|
||||
pr_info("ippm: tagmask 0x%x, rsvd %u=%u+%u+1, mask 0x%x,0x%x, "
|
||||
"pg %u,%u,%u,%u.\n",
|
||||
tagmask, tformat->rsvd_bits, tformat->idx_bits,
|
||||
tformat->color_bits, tformat->no_ddp_mask, tformat->rsvd_mask,
|
||||
tformat->pgsz_order[0], tformat->pgsz_order[1],
|
||||
tformat->pgsz_order[2], tformat->pgsz_order[3]);
|
||||
}
|
||||
|
||||
int cxgbi_ppm_find_page_index(struct cxgbi_ppm *ppm, unsigned long pgsz);
|
||||
void cxgbi_ppm_make_ppod_hdr(struct cxgbi_ppm *ppm, u32 tag,
|
||||
unsigned int tid, unsigned int offset,
|
||||
unsigned int length,
|
||||
struct cxgbi_pagepod_hdr *hdr);
|
||||
void cxgbi_ppm_ppod_release(struct cxgbi_ppm *, u32 idx);
|
||||
int cxgbi_ppm_ppods_reserve(struct cxgbi_ppm *, unsigned short nr_pages,
|
||||
u32 per_tag_pg_idx, u32 *ppod_idx, u32 *ddp_tag,
|
||||
unsigned long caller_data);
|
||||
int cxgbi_ppm_init(void **ppm_pp, struct net_device *, struct pci_dev *,
|
||||
void *lldev, struct cxgbi_tag_format *,
|
||||
unsigned int ppmax, unsigned int llimit,
|
||||
unsigned int start,
|
||||
unsigned int reserve_factor);
|
||||
int cxgbi_ppm_release(struct cxgbi_ppm *ppm);
|
||||
void cxgbi_tagmask_check(unsigned int tagmask, struct cxgbi_tag_format *);
|
||||
unsigned int cxgbi_tagmask_set(unsigned int ppmax);
|
||||
|
||||
#endif /*__CXGB4PPM_H__*/
|
||||
Loading…
Reference in New Issue
Block a user