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https://github.com/FEX-Emu/linux.git
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pinctrl: Add i.MX1 pincontrol driver
This patch adds pincontrol driver for Freescale i.MX1 SOCs. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Alexander Shiyan
Linus Walleij
parent
0d3bafac65
commit
4877e51ed7
@ -130,6 +130,13 @@ config PINCTRL_IMX1_CORE
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select PINMUX
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select PINCONF
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config PINCTRL_IMX1
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bool "IMX1 pinctrl driver"
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depends on SOC_IMX1
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select PINCTRL_IMX1_CORE
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help
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Say Y here to enable the imx1 pinctrl driver
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config PINCTRL_IMX27
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bool "IMX27 pinctrl driver"
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depends on SOC_IMX27
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@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
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obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
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obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
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obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
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obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
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obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
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obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
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obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
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279
drivers/pinctrl/pinctrl-imx1.c
Normal file
279
drivers/pinctrl/pinctrl-imx1.c
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@ -0,0 +1,279 @@
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/*
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* i.MX1 pinctrl driver based on imx pinmux core
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*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx1.h"
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#define PAD_ID(port, pin) ((port) * 32 + (pin))
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#define PA 0
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#define PB 1
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#define PC 2
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#define PD 3
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enum imx1_pads {
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MX1_PAD_A24 = PAD_ID(PA, 0),
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MX1_PAD_TIN = PAD_ID(PA, 1),
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MX1_PAD_PWMO = PAD_ID(PA, 2),
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MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
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MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
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MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
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MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
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MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
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MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
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MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
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MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
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MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
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MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
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MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
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MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
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MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
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MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
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MX1_PAD_DTACK = PAD_ID(PA, 17),
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MX1_PAD_BCLK = PAD_ID(PA, 18),
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MX1_PAD_LBA = PAD_ID(PA, 19),
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MX1_PAD_ECB = PAD_ID(PA, 20),
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MX1_PAD_A0 = PAD_ID(PA, 21),
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MX1_PAD_CS4 = PAD_ID(PA, 22),
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MX1_PAD_CS5 = PAD_ID(PA, 23),
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MX1_PAD_A16 = PAD_ID(PA, 24),
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MX1_PAD_A17 = PAD_ID(PA, 25),
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MX1_PAD_A18 = PAD_ID(PA, 26),
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MX1_PAD_A19 = PAD_ID(PA, 27),
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MX1_PAD_A20 = PAD_ID(PA, 28),
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MX1_PAD_A21 = PAD_ID(PA, 29),
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MX1_PAD_A22 = PAD_ID(PA, 30),
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MX1_PAD_A23 = PAD_ID(PA, 31),
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MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
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MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
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MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
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MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
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MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
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MX1_PAD_SD_CMD = PAD_ID(PB, 13),
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MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
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MX1_PAD_SIM_PD = PAD_ID(PB, 15),
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MX1_PAD_SIM_TX = PAD_ID(PB, 16),
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MX1_PAD_SIM_RX = PAD_ID(PB, 17),
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MX1_PAD_SIM_RST = PAD_ID(PB, 18),
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MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
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MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
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MX1_PAD_USBD_OE = PAD_ID(PB, 21),
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MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
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MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
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MX1_PAD_USBD_VP = PAD_ID(PB, 24),
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MX1_PAD_USBD_VM = PAD_ID(PB, 25),
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MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
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MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
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MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
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MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
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MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
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MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
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MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
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MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
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MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
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MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
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MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
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MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
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MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
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MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
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MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
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MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
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MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
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MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
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MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
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MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
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MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
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MX1_PAD_BT13 = PAD_ID(PC, 19),
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MX1_PAD_BT12 = PAD_ID(PC, 20),
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MX1_PAD_BT11 = PAD_ID(PC, 21),
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MX1_PAD_BT10 = PAD_ID(PC, 22),
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MX1_PAD_BT9 = PAD_ID(PC, 23),
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MX1_PAD_BT8 = PAD_ID(PC, 24),
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MX1_PAD_BT7 = PAD_ID(PC, 25),
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MX1_PAD_BT6 = PAD_ID(PC, 26),
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MX1_PAD_BT5 = PAD_ID(PC, 27),
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MX1_PAD_BT4 = PAD_ID(PC, 28),
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MX1_PAD_BT3 = PAD_ID(PC, 29),
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MX1_PAD_BT2 = PAD_ID(PC, 30),
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MX1_PAD_BT1 = PAD_ID(PC, 31),
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MX1_PAD_LSCLK = PAD_ID(PD, 6),
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MX1_PAD_REV = PAD_ID(PD, 7),
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MX1_PAD_CLS = PAD_ID(PD, 8),
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MX1_PAD_PS = PAD_ID(PD, 9),
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MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
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MX1_PAD_CONTRAST = PAD_ID(PD, 11),
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MX1_PAD_ACD_OE = PAD_ID(PD, 12),
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MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
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MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
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MX1_PAD_LD0 = PAD_ID(PD, 15),
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MX1_PAD_LD1 = PAD_ID(PD, 16),
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MX1_PAD_LD2 = PAD_ID(PD, 17),
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MX1_PAD_LD3 = PAD_ID(PD, 18),
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MX1_PAD_LD4 = PAD_ID(PD, 19),
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MX1_PAD_LD5 = PAD_ID(PD, 20),
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MX1_PAD_LD6 = PAD_ID(PD, 21),
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MX1_PAD_LD7 = PAD_ID(PD, 22),
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MX1_PAD_LD8 = PAD_ID(PD, 23),
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MX1_PAD_LD9 = PAD_ID(PD, 24),
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MX1_PAD_LD10 = PAD_ID(PD, 25),
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MX1_PAD_LD11 = PAD_ID(PD, 26),
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MX1_PAD_LD12 = PAD_ID(PD, 27),
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MX1_PAD_LD13 = PAD_ID(PD, 28),
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MX1_PAD_LD14 = PAD_ID(PD, 29),
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MX1_PAD_LD15 = PAD_ID(PD, 30),
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MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX1_PAD_A24),
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IMX_PINCTRL_PIN(MX1_PAD_TIN),
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IMX_PINCTRL_PIN(MX1_PAD_PWMO),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
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IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
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IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
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IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
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IMX_PINCTRL_PIN(MX1_PAD_DTACK),
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IMX_PINCTRL_PIN(MX1_PAD_BCLK),
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IMX_PINCTRL_PIN(MX1_PAD_LBA),
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IMX_PINCTRL_PIN(MX1_PAD_ECB),
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IMX_PINCTRL_PIN(MX1_PAD_A0),
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IMX_PINCTRL_PIN(MX1_PAD_CS4),
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IMX_PINCTRL_PIN(MX1_PAD_CS5),
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IMX_PINCTRL_PIN(MX1_PAD_A16),
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IMX_PINCTRL_PIN(MX1_PAD_A17),
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IMX_PINCTRL_PIN(MX1_PAD_A18),
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IMX_PINCTRL_PIN(MX1_PAD_A19),
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IMX_PINCTRL_PIN(MX1_PAD_A20),
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IMX_PINCTRL_PIN(MX1_PAD_A21),
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IMX_PINCTRL_PIN(MX1_PAD_A22),
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IMX_PINCTRL_PIN(MX1_PAD_A23),
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IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
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IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
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IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
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IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
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IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
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IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
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IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
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IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
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IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
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IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
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IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
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IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
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IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
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IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
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IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
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IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
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IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
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IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
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IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
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IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
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IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
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IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
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IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
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IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
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IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
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IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
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IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
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IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
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IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
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IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
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IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
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IMX_PINCTRL_PIN(MX1_PAD_BT13),
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IMX_PINCTRL_PIN(MX1_PAD_BT12),
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IMX_PINCTRL_PIN(MX1_PAD_BT11),
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IMX_PINCTRL_PIN(MX1_PAD_BT10),
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IMX_PINCTRL_PIN(MX1_PAD_BT9),
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IMX_PINCTRL_PIN(MX1_PAD_BT8),
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IMX_PINCTRL_PIN(MX1_PAD_BT7),
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IMX_PINCTRL_PIN(MX1_PAD_BT6),
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IMX_PINCTRL_PIN(MX1_PAD_BT5),
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IMX_PINCTRL_PIN(MX1_PAD_BT4),
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IMX_PINCTRL_PIN(MX1_PAD_BT3),
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IMX_PINCTRL_PIN(MX1_PAD_BT2),
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IMX_PINCTRL_PIN(MX1_PAD_BT1),
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IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
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IMX_PINCTRL_PIN(MX1_PAD_REV),
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IMX_PINCTRL_PIN(MX1_PAD_CLS),
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IMX_PINCTRL_PIN(MX1_PAD_PS),
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IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
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IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
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IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
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IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
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IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
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IMX_PINCTRL_PIN(MX1_PAD_LD0),
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IMX_PINCTRL_PIN(MX1_PAD_LD1),
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IMX_PINCTRL_PIN(MX1_PAD_LD2),
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IMX_PINCTRL_PIN(MX1_PAD_LD3),
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IMX_PINCTRL_PIN(MX1_PAD_LD4),
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IMX_PINCTRL_PIN(MX1_PAD_LD5),
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IMX_PINCTRL_PIN(MX1_PAD_LD6),
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IMX_PINCTRL_PIN(MX1_PAD_LD7),
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IMX_PINCTRL_PIN(MX1_PAD_LD8),
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IMX_PINCTRL_PIN(MX1_PAD_LD9),
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IMX_PINCTRL_PIN(MX1_PAD_LD10),
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IMX_PINCTRL_PIN(MX1_PAD_LD11),
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IMX_PINCTRL_PIN(MX1_PAD_LD12),
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IMX_PINCTRL_PIN(MX1_PAD_LD13),
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IMX_PINCTRL_PIN(MX1_PAD_LD14),
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IMX_PINCTRL_PIN(MX1_PAD_LD15),
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IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
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};
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static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
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.pins = imx1_pinctrl_pads,
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.npins = ARRAY_SIZE(imx1_pinctrl_pads),
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};
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static int __init imx1_pinctrl_probe(struct platform_device *pdev)
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{
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return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
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}
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static const struct of_device_id imx1_pinctrl_of_match[] = {
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{ .compatible = "fsl,imx1-iomuxc", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
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static struct platform_driver imx1_pinctrl_driver = {
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.driver = {
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.name = "imx1-pinctrl",
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.owner = THIS_MODULE,
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.of_match_table = imx1_pinctrl_of_match,
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},
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.remove = imx1_pinctrl_core_remove,
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};
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module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
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MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
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MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
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MODULE_LICENSE("GPL");
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