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drm/radeon/dpm: fix display gap programming on SI
Need to set the DISP*_GAP fields as well as the DISP*_GAP_MCHG fields. Same as on previous asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3620,8 +3620,12 @@ static void si_enable_display_gap(struct radeon_device *rdev)
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{
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u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
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tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
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tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
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DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
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tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
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tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
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tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
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DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
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WREG32(CG_DISPLAY_GAP_CNTL, tmp);
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}
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