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[ARM] 5284/1: pxa: cm-x255: add NOR and NAND flash support
This patch adds support for NOR and NAND flashes on CM-X255. The NAND flash support uses not yet merged GPIO NAND driver. Signed-off-by: Russ Dill <russ.dill@gmail.com> Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -12,6 +12,9 @@
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/nand-gpio.h>
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#include <linux/spi/spi.h>
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@ -26,6 +29,11 @@
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#include "generic.h"
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#define GPIO_NAND_CS (5)
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#define GPIO_NAND_ALE (4)
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#define GPIO_NAND_CLE (3)
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#define GPIO_NAND_RB (10)
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static unsigned long cmx255_pin_config[] = {
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/* AC'97 */
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GPIO28_AC97_BITCLK,
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@ -134,9 +142,117 @@ static void __init cmx255_init_rtc(void)
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static inline void cmx255_init_rtc(void) {}
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#endif
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#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
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static struct mtd_partition cmx255_nor_partitions[] = {
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{
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.name = "ARMmon",
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.size = 0x00030000,
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.offset = 0,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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} , {
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.name = "ARMmon setup block",
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.size = 0x00010000,
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.offset = MTDPART_OFS_APPEND,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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} , {
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.name = "kernel",
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.size = 0x00160000,
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.offset = MTDPART_OFS_APPEND,
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} , {
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.name = "ramdisk",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND
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}
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};
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static struct physmap_flash_data cmx255_nor_flash_data[] = {
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{
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.width = 2, /* bankwidth in bytes */
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.parts = cmx255_nor_partitions,
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.nr_parts = ARRAY_SIZE(cmx255_nor_partitions)
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}
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};
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static struct resource cmx255_nor_resource = {
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.start = PXA_CS0_PHYS,
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.end = PXA_CS0_PHYS + SZ_8M - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device cmx255_nor = {
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.name = "physmap-flash",
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.id = -1,
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.dev = {
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.platform_data = cmx255_nor_flash_data,
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},
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.resource = &cmx255_nor_resource,
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.num_resources = 1,
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};
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static void __init cmx255_init_nor(void)
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{
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platform_device_register(&cmx255_nor);
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}
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#else
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static inline void cmx255_init_nor(void) {}
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#endif
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#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
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static struct resource cmx255_nand_resource[] = {
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[0] = {
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.start = PXA_CS1_PHYS,
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.end = PXA_CS1_PHYS + 11,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PXA_CS5_PHYS,
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.end = PXA_CS5_PHYS + 3,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct mtd_partition cmx255_nand_parts[] = {
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[0] = {
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.name = "cmx255-nand",
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.size = MTDPART_SIZ_FULL,
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.offset = 0,
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},
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};
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static struct gpio_nand_platdata cmx255_nand_platdata = {
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.gpio_nce = GPIO_NAND_CS,
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.gpio_cle = GPIO_NAND_CLE,
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.gpio_ale = GPIO_NAND_ALE,
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.gpio_rdy = GPIO_NAND_RB,
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.gpio_nwp = -1,
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.parts = cmx255_nand_parts,
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.num_parts = ARRAY_SIZE(cmx255_nand_parts),
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.chip_delay = 25,
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};
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static struct platform_device cmx255_nand = {
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.name = "gpio-nand",
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.num_resources = ARRAY_SIZE(cmx255_nand_resource),
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.resource = cmx255_nand_resource,
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.id = -1,
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.dev = {
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.platform_data = &cmx255_nand_platdata,
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}
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};
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static void __init cmx255_init_nand(void)
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{
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platform_device_register(&cmx255_nand);
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}
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#else
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static inline void cmx255_init_nand(void) {}
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#endif
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void __init cmx255_init(void)
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{
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pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
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cmx255_init_rtc();
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cmx255_init_nor();
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cmx255_init_nand();
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}
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