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clk: qcom: Add EBI2 clocks for IPQ806x
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so that they can be used by the NAND controller driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -2172,6 +2172,36 @@ static struct clk_branch usb_fs1_h_clk = {
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},
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},
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};
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};
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static struct clk_branch ebi2_clk = {
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.hwcg_reg = 0x3b00,
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.hwcg_bit = 6,
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.halt_reg = 0x2fcc,
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.halt_bit = 1,
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.clkr = {
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.enable_reg = 0x3b00,
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "ebi2_clk",
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.ops = &clk_branch_ops,
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.flags = CLK_IS_ROOT,
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},
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},
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};
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static struct clk_branch ebi2_aon_clk = {
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.halt_reg = 0x2fcc,
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.halt_bit = 0,
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.clkr = {
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.enable_reg = 0x3b00,
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.enable_mask = BIT(8),
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.hw.init = &(struct clk_init_data){
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.name = "ebi2_always_on_clk",
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.ops = &clk_branch_ops,
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.flags = CLK_IS_ROOT,
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},
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},
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};
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static struct clk_regmap *gcc_ipq806x_clks[] = {
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static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL0] = &pll0.clkr,
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[PLL0] = &pll0.clkr,
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[PLL0_VOTE] = &pll0_vote,
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[PLL0_VOTE] = &pll0_vote,
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@ -2275,6 +2305,8 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
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[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
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[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
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[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
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[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
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[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
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[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
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[EBI2_CLK] = &ebi2_clk.clkr,
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[EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
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};
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};
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static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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@ -288,5 +288,6 @@
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#define UBI32_CORE2_CLK_SRC 278
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#define UBI32_CORE2_CLK_SRC 278
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#define UBI32_CORE1_CLK 279
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#define UBI32_CORE1_CLK 279
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#define UBI32_CORE2_CLK 280
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#define UBI32_CORE2_CLK 280
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#define EBI2_AON_CLK 281
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#endif
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#endif
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