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ARM: orion5x: Move to ID based window creation
With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
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c5d0ecc98c
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4ca2c04085
@ -174,7 +174,9 @@ void __init orion5x_xor_init(void)
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****************************************************************************/
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static void __init orion5x_crypto_init(void)
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{
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mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
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ORION_MBUS_SRAM_ATTR,
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ORION5X_SRAM_PHYS_BASE,
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ORION5X_SRAM_SIZE);
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orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
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SZ_8K, IRQ_ORION5X_CESA);
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@ -222,22 +224,24 @@ void orion5x_setup_wins(void)
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* The PCIe windows will no longer be statically allocated
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* here once Orion5x is migrated to the pci-mvebu driver.
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*/
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mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
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mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
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ORION_MBUS_PCIE_IO_ATTR,
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ORION5X_PCIE_IO_PHYS_BASE,
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ORION5X_PCIE_IO_SIZE,
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ORION5X_PCIE_IO_BUS_BASE,
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MVEBU_MBUS_PCI_IO);
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mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
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ORION5X_PCIE_MEM_SIZE,
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MVEBU_MBUS_NO_REMAP,
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MVEBU_MBUS_PCI_MEM);
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mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
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ORION5X_PCIE_IO_BUS_BASE);
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mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
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ORION_MBUS_PCIE_MEM_ATTR,
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ORION5X_PCIE_MEM_PHYS_BASE,
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ORION5X_PCIE_MEM_SIZE);
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mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
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ORION_MBUS_PCI_IO_ATTR,
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ORION5X_PCI_IO_PHYS_BASE,
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ORION5X_PCI_IO_SIZE,
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ORION5X_PCI_IO_BUS_BASE,
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MVEBU_MBUS_PCI_IO);
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mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
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ORION5X_PCI_MEM_SIZE,
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MVEBU_MBUS_NO_REMAP,
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MVEBU_MBUS_PCI_MEM);
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ORION5X_PCI_IO_BUS_BASE);
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mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
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ORION_MBUS_PCI_MEM_ATTR,
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ORION5X_PCI_MEM_PHYS_BASE,
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ORION5X_PCI_MEM_SIZE);
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}
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int orion5x_tclk;
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@ -7,6 +7,23 @@ struct dsa_platform_data;
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struct mv643xx_eth_platform_data;
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struct mv_sata_platform_data;
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#define ORION_MBUS_PCIE_MEM_TARGET 0x04
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#define ORION_MBUS_PCIE_MEM_ATTR 0x59
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#define ORION_MBUS_PCIE_IO_TARGET 0x04
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#define ORION_MBUS_PCIE_IO_ATTR 0x51
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#define ORION_MBUS_PCIE_WA_TARGET 0x04
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#define ORION_MBUS_PCIE_WA_ATTR 0x79
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#define ORION_MBUS_PCI_MEM_TARGET 0x03
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#define ORION_MBUS_PCI_MEM_ATTR 0x59
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#define ORION_MBUS_PCI_IO_TARGET 0x03
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#define ORION_MBUS_PCI_IO_ATTR 0x51
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#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
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#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
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#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
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#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
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#define ORION_MBUS_SRAM_TARGET 0x00
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#define ORION_MBUS_SRAM_ATTR 0x00
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/*
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* Basic Orion init functions used early by machine-setup.
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*/
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@ -317,7 +317,9 @@ static void __init d2net_init(void)
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d2net_sata_power_init();
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orion5x_sata_init(&d2net_sata_data);
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mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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D2NET_NOR_BOOT_BASE,
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D2NET_NOR_BOOT_SIZE);
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platform_device_register(&d2net_nor_flash);
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@ -340,18 +340,26 @@ static void __init db88f5281_init(void)
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orion5x_uart0_init();
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orion5x_uart1_init();
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mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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DB88F5281_NOR_BOOT_BASE,
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DB88F5281_NOR_BOOT_SIZE);
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platform_device_register(&db88f5281_boot_flash);
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mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
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ORION_MBUS_DEVBUS_ATTR(0),
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DB88F5281_7SEG_BASE,
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DB88F5281_7SEG_SIZE);
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mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
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ORION_MBUS_DEVBUS_ATTR(1),
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DB88F5281_NOR_BASE,
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DB88F5281_NOR_SIZE);
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platform_device_register(&db88f5281_nor_flash);
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mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
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ORION_MBUS_DEVBUS_ATTR(2),
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DB88F5281_NAND_BASE,
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DB88F5281_NAND_SIZE);
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platform_device_register(&db88f5281_nand_flash);
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@ -611,7 +611,9 @@ static void __init dns323_init(void)
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/* setup flash mapping
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* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
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*/
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mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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DNS323_NOR_BOOT_BASE,
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DNS323_NOR_BOOT_SIZE);
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platform_device_register(&dns323_nor_flash);
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@ -154,7 +154,9 @@ void __init edmini_v2_init(void)
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orion5x_ehci0_init();
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orion5x_eth_init(&edmini_v2_eth_data);
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mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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EDMINI_V2_NOR_BOOT_BASE,
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EDMINI_V2_NOR_BOOT_SIZE);
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platform_device_register(&edmini_v2_nor_flash);
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@ -359,12 +359,16 @@ static void __init kurobox_pro_init(void)
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orion5x_uart1_init();
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orion5x_xor_init();
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mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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KUROBOX_PRO_NOR_BOOT_BASE,
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KUROBOX_PRO_NOR_BOOT_SIZE);
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platform_device_register(&kurobox_pro_nor_flash);
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if (machine_is_kurobox_pro()) {
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mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
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ORION_MBUS_DEVBUS_ATTR(0),
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KUROBOX_PRO_NAND_BASE,
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KUROBOX_PRO_NAND_SIZE);
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platform_device_register(&kurobox_pro_nand_flash);
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}
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@ -294,7 +294,9 @@ static void __init lschl_init(void)
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orion5x_uart0_init();
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orion5x_xor_init();
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mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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LSCHL_NOR_BOOT_BASE,
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LSCHL_NOR_BOOT_SIZE);
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platform_device_register(&lschl_nor_flash);
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@ -243,7 +243,9 @@ static void __init ls_hgl_init(void)
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orion5x_uart0_init();
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orion5x_xor_init();
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mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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LS_HGL_NOR_BOOT_BASE,
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LS_HGL_NOR_BOOT_SIZE);
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platform_device_register(&ls_hgl_nor_flash);
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@ -244,7 +244,9 @@ static void __init lsmini_init(void)
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orion5x_uart0_init();
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orion5x_xor_init();
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mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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LSMINI_NOR_BOOT_BASE,
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LSMINI_NOR_BOOT_SIZE);
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platform_device_register(&lsmini_nor_flash);
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@ -241,7 +241,9 @@ static void __init mss2_init(void)
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orion5x_uart0_init();
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orion5x_xor_init();
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mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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MSS2_NOR_BOOT_BASE,
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MSS2_NOR_BOOT_SIZE);
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platform_device_register(&mss2_nor_flash);
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@ -204,7 +204,9 @@ static void __init mv2120_init(void)
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orion5x_uart0_init();
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orion5x_xor_init();
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mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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MV2120_NOR_BOOT_BASE,
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MV2120_NOR_BOOT_SIZE);
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platform_device_register(&mv2120_nor_flash);
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@ -397,7 +397,9 @@ static void __init net2big_init(void)
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net2big_sata_power_init();
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orion5x_sata_init(&net2big_sata_data);
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mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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NET2BIG_NOR_BOOT_BASE,
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NET2BIG_NOR_BOOT_SIZE);
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platform_device_register(&net2big_nor_flash);
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@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys)
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if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
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printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
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"read transaction workaround\n");
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mvebu_mbus_add_window_remap_flags("pcie0.0",
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mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
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ORION_MBUS_PCIE_WA_ATTR,
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ORION5X_PCIE_WA_PHYS_BASE,
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ORION5X_PCIE_WA_SIZE,
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MVEBU_MBUS_NO_REMAP,
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MVEBU_MBUS_PCI_WA);
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ORION5X_PCIE_WA_SIZE);
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pcie_ops.read = pcie_rd_conf_wa;
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}
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@ -123,7 +123,9 @@ static void __init rd88f5181l_fxo_init(void)
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orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
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orion5x_uart0_init();
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mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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RD88F5181L_FXO_NOR_BOOT_BASE,
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RD88F5181L_FXO_NOR_BOOT_SIZE);
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platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
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}
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@ -130,7 +130,9 @@ static void __init rd88f5181l_ge_init(void)
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orion5x_i2c_init();
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orion5x_uart0_init();
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mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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RD88F5181L_GE_NOR_BOOT_BASE,
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RD88F5181L_GE_NOR_BOOT_SIZE);
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platform_device_register(&rd88f5181l_ge_nor_boot_flash);
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@ -264,10 +264,13 @@ static void __init rd88f5182_init(void)
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orion5x_uart0_init();
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orion5x_xor_init();
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mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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RD88F5182_NOR_BOOT_BASE,
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RD88F5182_NOR_BOOT_SIZE);
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mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
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ORION_MBUS_DEVBUS_ATTR(1),
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RD88F5182_NOR_BASE,
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RD88F5182_NOR_SIZE);
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platform_device_register(&rd88f5182_nor_flash);
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platform_device_register(&rd88f5182_gpio_leds);
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@ -329,7 +329,9 @@ static void __init tsp2_init(void)
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/*
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* Configure peripherals.
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*/
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mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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TSP2_NOR_BOOT_BASE,
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TSP2_NOR_BOOT_SIZE);
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platform_device_register(&tsp2_nor_flash);
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@ -286,7 +286,9 @@ static void __init qnap_ts209_init(void)
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/*
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* Configure peripherals.
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*/
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mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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QNAP_TS209_NOR_BOOT_BASE,
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QNAP_TS209_NOR_BOOT_SIZE);
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platform_device_register(&qnap_ts209_nor_flash);
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@ -277,7 +277,9 @@ static void __init qnap_ts409_init(void)
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/*
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* Configure peripherals.
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*/
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mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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QNAP_TS409_NOR_BOOT_BASE,
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QNAP_TS409_NOR_BOOT_SIZE);
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platform_device_register(&qnap_ts409_nor_flash);
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@ -127,7 +127,9 @@ static void __init wnr854t_init(void)
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orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
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orion5x_uart0_init();
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mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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WNR854T_NOR_BOOT_BASE,
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WNR854T_NOR_BOOT_SIZE);
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platform_device_register(&wnr854t_nor_flash);
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}
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@ -213,7 +213,9 @@ static void __init wrt350n_v2_init(void)
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orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
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orion5x_uart0_init();
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mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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WRT350N_V2_NOR_BOOT_BASE,
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WRT350N_V2_NOR_BOOT_SIZE);
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platform_device_register(&wrt350n_v2_nor_flash);
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platform_device_register(&wrt350n_v2_leds);
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