mirror of
https://github.com/FEX-Emu/linux.git
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ARM: SoC: late updates
This is some material that we picked up into our tree late, or that had
more complex dependencies on more than one topic branch that makes sense
to keep separately.
- TI support for secure accelerators and hwrng on OMAP4/5
- TI camera changes for dra7 and am437x and SGX improvement due to better
reset control support on am335x, am437x and dra7
- Davinci moves to proper clocksource on DM365, and regulator/audio
improvements for DM365 and DM644x eval boards
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC late updates from Olof Johansson:
"This is some material that we picked up into our tree late, or that
had more complex dependencies on more than one topic branch that makes
sense to keep separately.
- TI support for secure accelerators and hwrng on OMAP4/5
- TI camera changes for dra7 and am437x and SGX improvement due to
better reset control support on am335x, am437x and dra7
- Davinci moves to proper clocksource on DM365, and regulator/audio
improvements for DM365 and DM644x eval boards"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits)
ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem
ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt
ARM: dts: Configure interconnect target module for am437x sgx
ARM: dts: Configure sgx for dra7
ARM: dts: Configure rstctrl reset for am335x SGX
ARM: dts: dra7: Add ti-sysc node for VPE
ARM: dts: dra7: add vpe clkctrl node
ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries
ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries
ARM: dts: am43xx: add support for clkout1 clock
arm: dts: dra76-evm: Add CAL and OV5640 nodes
arm: dtsi: dra76x: Add CAL dtsi node
arm: dts: dra72-evm-common: Add entries for the CSI2 cameras
ARM: dts: DRA72: Add CAL dtsi node
ARM: dts: dra7-l4: Add ti-sysc node for CAM
ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only
ARM: dts: dra7: add cam clkctrl node
ARM: OMAP2+: Drop legacy platform data for omap4 des
ARM: OMAP2+: Drop legacy platform data for omap4 sham
ARM: OMAP2+: Drop legacy platform data for omap4 aes
...
This commit is contained in:
Linus Torvalds
commit
4ef1a30c6b
@ -496,6 +496,31 @@
|
||||
dma-names = "tx", "rx";
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};
|
||||
};
|
||||
|
||||
target-module@56000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5600fe00 0x4>,
|
||||
<0x5600fe10 0x4>;
|
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reg-names = "rev", "sysc";
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||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>;
|
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clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
|
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clock-names = "fck";
|
||||
resets = <&prm_gfx 0>;
|
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reset-names = "rstctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x1000000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
};
|
||||
};
|
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};
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@ -445,6 +445,26 @@
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pool;
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||||
};
|
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};
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|
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target-module@56000000 {
|
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compatible = "ti,sysc-omap4", "ti,sysc";
|
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reg = <0x5600fe00 0x4>,
|
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<0x5600fe10 0x4>;
|
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>;
|
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>;
|
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clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
resets = <&prm_gfx 0>;
|
||||
reset-names = "rstctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -272,6 +272,12 @@
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>;
|
||||
};
|
||||
|
||||
clkout1_pin: pinmux_clkout1_pin {
|
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pinctrl-single,pins = <
|
||||
0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
@ -593,6 +599,25 @@
|
||||
pinctrl-0 = <&i2c1_pins>;
|
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clock-frequency = <400000>;
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||||
|
||||
ov2659@30 {
|
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compatible = "ovti,ov2659";
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reg = <0x30>;
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pinctrl-names = "default";
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pinctrl-0 = <&clkout1_pin>;
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clocks = <&clkout1_mux_ck>;
|
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clock-names = "xvclk";
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assigned-clocks = <&clkout1_mux_ck>;
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assigned-clock-parents = <&clkout1_osc_div_ck>;
|
||||
|
||||
port {
|
||||
ov2659_1: endpoint {
|
||||
remote-endpoint = <&vpfe0_ep>;
|
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link-frequencies = /bits/ 64 <70000000>;
|
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};
|
||||
};
|
||||
};
|
||||
|
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edt-ft5306@38 {
|
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status = "okay";
|
||||
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
|
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@ -877,7 +902,7 @@
|
||||
/* Camera port */
|
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port {
|
||||
vpfe0_ep: endpoint {
|
||||
/* remote-endpoint = <&sensor>; add once we have it */
|
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remote-endpoint = <&ov2659_1>;
|
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ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
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hsync-active = <0>;
|
||||
|
||||
@ -145,6 +145,12 @@
|
||||
system-clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
audio_mstrclk: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&am43xx_pinmux {
|
||||
@ -696,6 +702,21 @@
|
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IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
|
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DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
|
||||
};
|
||||
|
||||
ov2659@30 {
|
||||
compatible = "ovti,ov2659";
|
||||
reg = <0x30>;
|
||||
|
||||
clocks = <&audio_mstrclk>;
|
||||
clock-names = "xvclk";
|
||||
|
||||
port {
|
||||
ov2659_1: endpoint {
|
||||
remote-endpoint = <&vpfe1_ep>;
|
||||
link-frequencies = /bits/ 64 <70000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
@ -964,7 +985,7 @@
|
||||
|
||||
port {
|
||||
vpfe1_ep: endpoint {
|
||||
/* remote-endpoint = <&sensor>; add once we have it */
|
||||
remote-endpoint = <&ov2659_1>;
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
|
||||
@ -704,6 +704,60 @@
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a48>;
|
||||
};
|
||||
|
||||
clkout1_osc_div_ck: clkout1-osc-div-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
ti,bit-shift = <20>;
|
||||
ti,max-div = <4>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_src2_mux_ck: clkout1-src2-mux-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
|
||||
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
|
||||
<&dpll_mpu_m2_ck>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&clkout1_src2_mux_ck>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <8>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
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clocks = <&clkout1_src2_pre_div_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
ti,max-div = <32>;
|
||||
ti,index-power-of-two;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_mux_ck: clkout1-mux-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
|
||||
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
|
||||
ti,bit-shift = <16>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_ck: clkout1-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkout1_mux_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
};
|
||||
|
||||
&prcm {
|
||||
|
||||
@ -4176,35 +4176,88 @@
|
||||
};
|
||||
|
||||
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x170010 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x170000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x190010 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x190000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x1b0000 0x4>,
|
||||
<0x1b0010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1b0000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x1d0010 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1d0000 0x10000>;
|
||||
|
||||
vpe: vpe@0 {
|
||||
compatible = "ti,dra7-vpe";
|
||||
reg = <0x0000 0x120>,
|
||||
<0x0700 0x80>,
|
||||
<0x5700 0x18>,
|
||||
<0xd000 0x400>;
|
||||
reg-names = "vpe_top",
|
||||
"sc",
|
||||
"csc",
|
||||
"vpdma";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -673,6 +673,24 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@56000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5600fe00 0x4>,
|
||||
<0x5600fe10 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x2000000>;
|
||||
};
|
||||
|
||||
crossbar_mpu: crossbar@4a002a48 {
|
||||
compatible = "ti,irq-crossbar";
|
||||
reg = <0x4a002a48 0x130>;
|
||||
|
||||
@ -187,6 +187,12 @@
|
||||
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
@ -269,6 +275,23 @@
|
||||
line-name = "vin6_sel_s0";
|
||||
};
|
||||
};
|
||||
|
||||
ov5640@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2_phy0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
@ -580,3 +603,11 @@
|
||||
&pcie1_rc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_0 {
|
||||
csi2_phy0: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -17,6 +17,48 @@
|
||||
};
|
||||
};
|
||||
|
||||
&l4_per2 {
|
||||
target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5b000 0x4>,
|
||||
<0x5b010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x5b000 0x1000>;
|
||||
|
||||
cal: cal@0 {
|
||||
compatible = "ti,dra72-cal";
|
||||
reg = <0x0000 0x400>,
|
||||
<0x0800 0x40>,
|
||||
<0x0900 0x40>;
|
||||
reg-names = "cal_top",
|
||||
"cal_rx_core0",
|
||||
"cal_rx_core1";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,camerrx-control = <&scm_conf 0xE94>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi2_0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
csi2_1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
reg = <0x58000000 0x80>,
|
||||
<0x58004054 0x4>,
|
||||
|
||||
@ -124,6 +124,12 @@
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
@ -366,6 +372,27 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ov5640@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2_phy0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
vdd-supply = <&buck10_reg>;
|
||||
};
|
||||
@ -513,3 +540,11 @@
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_0 {
|
||||
csi2_phy0: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -41,6 +41,48 @@
|
||||
|
||||
};
|
||||
|
||||
&l4_per3 {
|
||||
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x1b0000 0x4>,
|
||||
<0x1b0010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1b0000 0x10000>;
|
||||
|
||||
cal: cal@0 {
|
||||
compatible = "ti,dra76-cal";
|
||||
reg = <0x0000 0x400>,
|
||||
<0x0800 0x40>,
|
||||
<0x0900 0x40>;
|
||||
reg-names = "cal_top",
|
||||
"cal_rx_core0",
|
||||
"cal_rx_core1";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,camerrx-control = <&scm_conf 0x6dc>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi2_0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
csi2_1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* MCAN interrupts are hard-wired to irqs 67, 68 */
|
||||
&crossbar_mpu {
|
||||
ti,irqs-skip = <10 67 68 133 139 140>;
|
||||
|
||||
@ -1591,10 +1591,10 @@
|
||||
|
||||
rtc_cm: rtc-cm@700 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x700 0x100>;
|
||||
reg = <0x700 0x60>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x700 0x100>;
|
||||
ranges = <0 0x700 0x60>;
|
||||
|
||||
rtc_clkctrl: rtc-clkctrl@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
@ -1603,6 +1603,20 @@
|
||||
};
|
||||
};
|
||||
|
||||
vpe_cm: vpe-cm@760 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x760 0xc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x760 0xc>;
|
||||
|
||||
vpe_clkctrl: vpe-clkctrl@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x0 0xc>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&cm_core {
|
||||
@ -1720,6 +1734,20 @@
|
||||
};
|
||||
};
|
||||
|
||||
cam_cm: cam-cm@1000 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1000 0x100>;
|
||||
|
||||
cam_clkctrl: cam-clkctrl@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x2c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dss_cm: dss-cm@1100 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1100 0x100>;
|
||||
|
||||
@ -27,11 +27,12 @@
|
||||
compatible = "motorola,cpcap-battery";
|
||||
interrupts-extended = <
|
||||
&cpcap 6 0 &cpcap 5 0 &cpcap 3 0
|
||||
&cpcap 20 0 &cpcap 54 0
|
||||
&cpcap 20 0 &cpcap 54 0 &cpcap 57 0
|
||||
>;
|
||||
interrupt-names =
|
||||
"eol", "lowbph", "lowbpl",
|
||||
"chrgcurr1", "battdetb";
|
||||
"chrgcurr1", "battdetb",
|
||||
"cccal";
|
||||
io-channels = <&cpcap_adc 0 &cpcap_adc 1
|
||||
&cpcap_adc 5 &cpcap_adc 6>;
|
||||
io-channel-names = "battdetb", "battp",
|
||||
|
||||
@ -249,6 +249,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
/* Battery NVRAM on 1-wire handled by w1_ds250x driver */
|
||||
&hdqw1w {
|
||||
pinctrl-0 = <&hdq_pins>;
|
||||
pinctrl-names = "default";
|
||||
ti,mode = "1w";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
tmp105@48 {
|
||||
compatible = "ti,tmp105";
|
||||
@ -440,6 +447,13 @@
|
||||
>;
|
||||
};
|
||||
|
||||
hdq_pins: pinmux_hdq_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* 0x4a100120 hdq_sio.hdq_sio aa27 */
|
||||
OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0)
|
||||
>;
|
||||
};
|
||||
|
||||
/* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
|
||||
dss_hdmi_pins: pinmux_dss_hdmi_pins {
|
||||
pinctrl-single,pins = <
|
||||
@ -650,6 +664,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
/* RNG is used by secure mode and not accessible */
|
||||
&rng_target {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Configure pwm clock source for timers 8 & 9 */
|
||||
&timer8 {
|
||||
assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
|
||||
|
||||
@ -1990,12 +1990,26 @@
|
||||
};
|
||||
};
|
||||
|
||||
target-module@90000 { /* 0x48090000, ap 57 2a.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x91fe0 0x4>,
|
||||
<0x91fe4 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
||||
clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x90000 0x2000>;
|
||||
|
||||
rng: rng@0 {
|
||||
compatible = "ti,omap4-rng";
|
||||
reg = <0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@96000 { /* 0x48096000, ap 37 26.0 */
|
||||
@ -2159,6 +2173,35 @@
|
||||
<0x00001000 0x000a5000 0x00001000>;
|
||||
};
|
||||
|
||||
des_target: target-module@a5000 { /* 0x480a5000 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0xa5030 0x4>,
|
||||
<0xa5034 0x4>,
|
||||
<0xa5038 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,syss-mask = <1>;
|
||||
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
||||
clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xa5000 0x00001000>;
|
||||
|
||||
des: des@0 {
|
||||
compatible = "ti,omap4-des";
|
||||
reg = <0 0xa0>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 117>, <&sdma 116>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
|
||||
@ -278,40 +278,90 @@
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
|
||||
aes1: aes@4b501000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes1";
|
||||
reg = <0x4b501000 0xa0>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 111>, <&sdma 110>;
|
||||
dma-names = "tx", "rx";
|
||||
aes1_target: target-module@4b501000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x4b501080 0x4>,
|
||||
<0x4b501084 0x4>,
|
||||
<0x4b501088 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,syss-mask = <1>;
|
||||
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
||||
clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4b501000 0x1000>;
|
||||
|
||||
aes1: aes@0 {
|
||||
compatible = "ti,omap4-aes";
|
||||
reg = <0 0xa0>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 111>, <&sdma 110>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
|
||||
aes2: aes@4b701000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes2";
|
||||
reg = <0x4b701000 0xa0>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 114>, <&sdma 113>;
|
||||
dma-names = "tx", "rx";
|
||||
aes2_target: target-module@4b701000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x4b701080 0x4>,
|
||||
<0x4b701084 0x4>,
|
||||
<0x4b701088 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,syss-mask = <1>;
|
||||
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
||||
clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4b701000 0x1000>;
|
||||
|
||||
aes2: aes@0 {
|
||||
compatible = "ti,omap4-aes";
|
||||
reg = <0 0xa0>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 114>, <&sdma 113>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
|
||||
des: des@480a5000 {
|
||||
compatible = "ti,omap4-des";
|
||||
ti,hwmods = "des";
|
||||
reg = <0x480a5000 0xa0>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 117>, <&sdma 116>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
sham_target: target-module@4b100000 {
|
||||
compatible = "ti,sysc-omap3-sham", "ti,sysc";
|
||||
reg = <0x4b100100 0x4>,
|
||||
<0x4b100110 0x4>,
|
||||
<0x4b100114 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,syss-mask = <1>;
|
||||
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
||||
clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4b100000 0x1000>;
|
||||
|
||||
sham: sham@4b100000 {
|
||||
compatible = "ti,omap4-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x4b100000 0x300>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 119>;
|
||||
dma-names = "rx";
|
||||
sham: sham@0 {
|
||||
compatible = "ti,omap4-sham";
|
||||
reg = <0 0x300>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 119>;
|
||||
dma-names = "rx";
|
||||
};
|
||||
};
|
||||
|
||||
abb_mpu: regulator-abb-mpu {
|
||||
|
||||
@ -1279,13 +1279,18 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1400 0x200>;
|
||||
|
||||
l4_per_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
l4_per_clkctrl: clock@20 {
|
||||
compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
|
||||
reg = <0x20 0x144>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l4_secure_clkctrl: clock@1a0 {
|
||||
compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
|
||||
reg = <0x1a0 0x3c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&prm {
|
||||
|
||||
@ -1764,12 +1764,26 @@
|
||||
};
|
||||
};
|
||||
|
||||
target-module@90000 { /* 0x48090000, ap 55 1a.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x91fe0 0x4>,
|
||||
<0x91fe4 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
|
||||
clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x90000 0x2000>;
|
||||
|
||||
rng: rng@0 {
|
||||
compatible = "ti,omap4-rng";
|
||||
reg = <0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@98000 { /* 0x48098000, ap 47 08.0 */
|
||||
|
||||
@ -1125,11 +1125,17 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1000 0x200>;
|
||||
|
||||
l4per_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
l4per_clkctrl: clock@20 {
|
||||
compatible = "ti,clkctrl-l4per", "ti,clkctrl";
|
||||
reg = <0x20 0x15c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
l4sec_clkctrl: clock@1a0 {
|
||||
compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
|
||||
reg = <0x1a0 0x3c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dss_cm: dss_cm@1400 {
|
||||
|
||||
@ -7,8 +7,7 @@
|
||||
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
|
||||
# Common objects
|
||||
obj-y := time.o serial.o usb.o \
|
||||
common.o sram.o
|
||||
obj-y := serial.o usb.o common.o sram.o
|
||||
|
||||
obj-$(CONFIG_DAVINCI_MUX) += mux.o
|
||||
|
||||
|
||||
@ -30,6 +30,8 @@
|
||||
#include <linux/spi/eeprom.h>
|
||||
#include <linux/v4l2-dv-timings.h>
|
||||
#include <linux/platform_data/ti-aemif.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
@ -245,6 +247,19 @@ static struct davinci_i2c_platform_data i2c_pdata = {
|
||||
.bus_delay = 0 /* usec */,
|
||||
};
|
||||
|
||||
/* Fixed regulator support */
|
||||
static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
|
||||
/* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
|
||||
REGULATOR_SUPPLY("AVDD", "1-0018"),
|
||||
REGULATOR_SUPPLY("DRVDD", "1-0018"),
|
||||
REGULATOR_SUPPLY("IOVDD", "1-0018"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
|
||||
/* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
|
||||
REGULATOR_SUPPLY("DVDD", "1-0018"),
|
||||
};
|
||||
|
||||
static int dm365evm_keyscan_enable(struct device *dev)
|
||||
{
|
||||
return davinci_cfg_reg(DM365_KEYSCAN);
|
||||
@ -800,6 +815,11 @@ static __init void dm365_evm_init(void)
|
||||
if (ret)
|
||||
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
|
||||
|
||||
regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
|
||||
ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
|
||||
regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
|
||||
ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
|
||||
|
||||
nvmem_add_cell_table(&davinci_nvmem_cell_table);
|
||||
nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
|
||||
|
||||
|
||||
@ -29,6 +29,8 @@
|
||||
#include <linux/v4l2-dv-timings.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
#include <media/i2c/tvp514x.h>
|
||||
|
||||
@ -653,6 +655,19 @@ static struct i2c_board_info __initdata i2c_info[] = {
|
||||
},
|
||||
};
|
||||
|
||||
/* Fixed regulator support */
|
||||
static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
|
||||
/* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
|
||||
REGULATOR_SUPPLY("AVDD", "1-001b"),
|
||||
REGULATOR_SUPPLY("DRVDD", "1-001b"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
|
||||
/* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
|
||||
REGULATOR_SUPPLY("IOVDD", "1-001b"),
|
||||
REGULATOR_SUPPLY("DVDD", "1-001b"),
|
||||
};
|
||||
|
||||
#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
|
||||
#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
|
||||
|
||||
@ -842,6 +857,11 @@ static __init void davinci_evm_init(void)
|
||||
|
||||
dm644x_register_clocks();
|
||||
|
||||
regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
|
||||
ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
|
||||
regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
|
||||
ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
|
||||
|
||||
dm644x_init_devices();
|
||||
|
||||
ret = dm644x_gpio_register();
|
||||
|
||||
@ -21,7 +21,6 @@
|
||||
#include <mach/common.h>
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/da8xx.h>
|
||||
#include <mach/time.h>
|
||||
|
||||
#include "asp.h"
|
||||
#include "cpuidle.h"
|
||||
|
||||
@ -17,7 +17,6 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/time.h>
|
||||
|
||||
#include "davinci.h"
|
||||
#include "irqs.h"
|
||||
@ -303,21 +302,3 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata)
|
||||
davinci_gpio_device.dev.platform_data = pdata;
|
||||
return platform_device_register(&davinci_gpio_device);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
struct davinci_timer_instance davinci_timer_instance[2] = {
|
||||
{
|
||||
.base = DAVINCI_TIMER0_BASE,
|
||||
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12),
|
||||
.top_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34),
|
||||
},
|
||||
{
|
||||
.base = DAVINCI_TIMER1_BASE,
|
||||
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12),
|
||||
.top_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34),
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
@ -35,7 +35,8 @@
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/serial.h>
|
||||
#include <mach/time.h>
|
||||
|
||||
#include <clocksource/timer-davinci.h>
|
||||
|
||||
#include "asp.h"
|
||||
#include "davinci.h"
|
||||
@ -660,10 +661,16 @@ static struct davinci_id dm365_ids[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct davinci_timer_info dm365_timer_info = {
|
||||
.timers = davinci_timer_instance,
|
||||
.clockevent_id = T0_BOT,
|
||||
.clocksource_id = T0_TOP,
|
||||
/*
|
||||
* Bottom half of timer0 is used for clockevent, top half is used for
|
||||
* clocksource.
|
||||
*/
|
||||
static const struct davinci_timer_cfg dm365_timer_cfg = {
|
||||
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
|
||||
.irq = {
|
||||
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
|
||||
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
|
||||
},
|
||||
};
|
||||
|
||||
#define DM365_UART1_BASE (IO_PHYS + 0x106000)
|
||||
@ -723,7 +730,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
|
||||
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
|
||||
.pinmux_pins = dm365_pins,
|
||||
.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
|
||||
.timer_info = &dm365_timer_info,
|
||||
.emac_pdata = &dm365_emac_pdata,
|
||||
.sram_dma = 0x00010000,
|
||||
.sram_len = SZ_32K,
|
||||
@ -771,6 +777,7 @@ void __init dm365_init_time(void)
|
||||
{
|
||||
void __iomem *pll1, *pll2, *psc;
|
||||
struct clk *clk;
|
||||
int rv;
|
||||
|
||||
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
|
||||
|
||||
@ -789,7 +796,8 @@ void __init dm365_init_time(void)
|
||||
return;
|
||||
}
|
||||
|
||||
davinci_timer_init(clk);
|
||||
rv = davinci_timer_register(clk, &dm365_timer_cfg);
|
||||
WARN(rv, "Unable to register the timer: %d\n", rv);
|
||||
}
|
||||
|
||||
void __init dm365_register_clocks(void)
|
||||
|
||||
@ -22,22 +22,6 @@
|
||||
#define DAVINCI_INTC_START NR_IRQS
|
||||
#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
|
||||
|
||||
void davinci_timer_init(struct clk *clk);
|
||||
|
||||
struct davinci_timer_instance {
|
||||
u32 base;
|
||||
u32 bottom_irq;
|
||||
u32 top_irq;
|
||||
unsigned long cmp_off;
|
||||
unsigned int cmp_irq;
|
||||
};
|
||||
|
||||
struct davinci_timer_info {
|
||||
struct davinci_timer_instance *timers;
|
||||
unsigned int clockevent_id;
|
||||
unsigned int clocksource_id;
|
||||
};
|
||||
|
||||
struct davinci_gpio_controller;
|
||||
|
||||
/*
|
||||
@ -58,7 +42,6 @@ struct davinci_soc_info {
|
||||
u32 pinmux_base;
|
||||
const struct mux_config *pinmux_pins;
|
||||
unsigned long pinmux_pins_num;
|
||||
struct davinci_timer_info *timer_info;
|
||||
int gpio_type;
|
||||
u32 gpio_base;
|
||||
unsigned gpio_num;
|
||||
|
||||
@ -1,33 +0,0 @@
|
||||
/*
|
||||
* Local header file for DaVinci time code.
|
||||
*
|
||||
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
|
||||
#define __ARCH_ARM_MACH_DAVINCI_TIME_H
|
||||
|
||||
#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
|
||||
|
||||
enum {
|
||||
T0_BOT,
|
||||
T0_TOP,
|
||||
T1_BOT,
|
||||
T1_TOP,
|
||||
NUM_TIMERS
|
||||
};
|
||||
|
||||
#define IS_TIMER1(id) (id & 0x2)
|
||||
#define IS_TIMER0(id) (!IS_TIMER1(id))
|
||||
#define IS_TIMER_TOP(id) ((id & 0x1))
|
||||
#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
|
||||
|
||||
#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0)
|
||||
|
||||
extern struct davinci_timer_instance davinci_timer_instance[];
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
|
||||
@ -1,400 +0,0 @@
|
||||
/*
|
||||
* DaVinci timer subsystem
|
||||
*
|
||||
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/sched_clock.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/time.h>
|
||||
|
||||
static struct clock_event_device clockevent_davinci;
|
||||
static unsigned int davinci_clock_tick_rate;
|
||||
|
||||
/*
|
||||
* This driver configures the 2 64-bit count-up timers as 4 independent
|
||||
* 32-bit count-up timers used as follows:
|
||||
*/
|
||||
|
||||
enum {
|
||||
TID_CLOCKEVENT,
|
||||
TID_CLOCKSOURCE,
|
||||
};
|
||||
|
||||
/* Timer register offsets */
|
||||
#define PID12 0x0
|
||||
#define TIM12 0x10
|
||||
#define TIM34 0x14
|
||||
#define PRD12 0x18
|
||||
#define PRD34 0x1c
|
||||
#define TCR 0x20
|
||||
#define TGCR 0x24
|
||||
#define WDTCR 0x28
|
||||
|
||||
/* Offsets of the 8 compare registers */
|
||||
#define CMP12_0 0x60
|
||||
#define CMP12_1 0x64
|
||||
#define CMP12_2 0x68
|
||||
#define CMP12_3 0x6c
|
||||
#define CMP12_4 0x70
|
||||
#define CMP12_5 0x74
|
||||
#define CMP12_6 0x78
|
||||
#define CMP12_7 0x7c
|
||||
|
||||
/* Timer register bitfields */
|
||||
#define TCR_ENAMODE_DISABLE 0x0
|
||||
#define TCR_ENAMODE_ONESHOT 0x1
|
||||
#define TCR_ENAMODE_PERIODIC 0x2
|
||||
#define TCR_ENAMODE_MASK 0x3
|
||||
|
||||
#define TGCR_TIMMODE_SHIFT 2
|
||||
#define TGCR_TIMMODE_64BIT_GP 0x0
|
||||
#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
|
||||
#define TGCR_TIMMODE_64BIT_WDOG 0x2
|
||||
#define TGCR_TIMMODE_32BIT_CHAINED 0x3
|
||||
|
||||
#define TGCR_TIM12RS_SHIFT 0
|
||||
#define TGCR_TIM34RS_SHIFT 1
|
||||
#define TGCR_RESET 0x0
|
||||
#define TGCR_UNRESET 0x1
|
||||
#define TGCR_RESET_MASK 0x3
|
||||
|
||||
struct timer_s {
|
||||
char *name;
|
||||
unsigned int id;
|
||||
unsigned long period;
|
||||
unsigned long opts;
|
||||
unsigned long flags;
|
||||
void __iomem *base;
|
||||
unsigned long tim_off;
|
||||
unsigned long prd_off;
|
||||
unsigned long enamode_shift;
|
||||
struct irqaction irqaction;
|
||||
};
|
||||
static struct timer_s timers[];
|
||||
|
||||
/* values for 'opts' field of struct timer_s */
|
||||
#define TIMER_OPTS_DISABLED 0x01
|
||||
#define TIMER_OPTS_ONESHOT 0x02
|
||||
#define TIMER_OPTS_PERIODIC 0x04
|
||||
#define TIMER_OPTS_STATE_MASK 0x07
|
||||
|
||||
#define TIMER_OPTS_USE_COMPARE 0x80000000
|
||||
#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE)
|
||||
|
||||
static char *id_to_name[] = {
|
||||
[T0_BOT] = "timer0_0",
|
||||
[T0_TOP] = "timer0_1",
|
||||
[T1_BOT] = "timer1_0",
|
||||
[T1_TOP] = "timer1_1",
|
||||
};
|
||||
|
||||
static int timer32_config(struct timer_s *t)
|
||||
{
|
||||
u32 tcr;
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
|
||||
if (USING_COMPARE(t)) {
|
||||
struct davinci_timer_instance *dtip =
|
||||
soc_info->timer_info->timers;
|
||||
int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
|
||||
|
||||
/*
|
||||
* Next interrupt should be the current time reg value plus
|
||||
* the new period (using 32-bit unsigned addition/wrapping
|
||||
* to 0 on overflow). This assumes that the clocksource
|
||||
* is setup to count to 2^32-1 before wrapping around to 0.
|
||||
*/
|
||||
__raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
|
||||
t->base + dtip[event_timer].cmp_off);
|
||||
} else {
|
||||
tcr = __raw_readl(t->base + TCR);
|
||||
|
||||
/* disable timer */
|
||||
tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
|
||||
__raw_writel(tcr, t->base + TCR);
|
||||
|
||||
/* reset counter to zero, set new period */
|
||||
__raw_writel(0, t->base + t->tim_off);
|
||||
__raw_writel(t->period, t->base + t->prd_off);
|
||||
|
||||
/* Set enable mode */
|
||||
if (t->opts & TIMER_OPTS_ONESHOT)
|
||||
tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
|
||||
else if (t->opts & TIMER_OPTS_PERIODIC)
|
||||
tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
|
||||
|
||||
__raw_writel(tcr, t->base + TCR);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline u32 timer32_read(struct timer_s *t)
|
||||
{
|
||||
return __raw_readl(t->base + t->tim_off);
|
||||
}
|
||||
|
||||
static irqreturn_t timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &clockevent_davinci;
|
||||
|
||||
evt->event_handler(evt);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* called when 32-bit counter wraps */
|
||||
static irqreturn_t freerun_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct timer_s timers[] = {
|
||||
[TID_CLOCKEVENT] = {
|
||||
.name = "clockevent",
|
||||
.opts = TIMER_OPTS_DISABLED,
|
||||
.irqaction = {
|
||||
.flags = IRQF_TIMER,
|
||||
.handler = timer_interrupt,
|
||||
}
|
||||
},
|
||||
[TID_CLOCKSOURCE] = {
|
||||
.name = "free-run counter",
|
||||
.period = ~0,
|
||||
.opts = TIMER_OPTS_PERIODIC,
|
||||
.irqaction = {
|
||||
.flags = IRQF_TIMER,
|
||||
.handler = freerun_interrupt,
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
static void __init timer_init(void)
|
||||
{
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
|
||||
void __iomem *base[2];
|
||||
int i;
|
||||
|
||||
/* Global init of each 64-bit timer as a whole */
|
||||
for(i=0; i<2; i++) {
|
||||
u32 tgcr;
|
||||
|
||||
base[i] = ioremap(dtip[i].base, SZ_4K);
|
||||
if (WARN_ON(!base[i]))
|
||||
continue;
|
||||
|
||||
/* Disabled, Internal clock source */
|
||||
__raw_writel(0, base[i] + TCR);
|
||||
|
||||
/* reset both timers, no pre-scaler for timer34 */
|
||||
tgcr = 0;
|
||||
__raw_writel(tgcr, base[i] + TGCR);
|
||||
|
||||
/* Set both timers to unchained 32-bit */
|
||||
tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
|
||||
__raw_writel(tgcr, base[i] + TGCR);
|
||||
|
||||
/* Unreset timers */
|
||||
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
|
||||
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
|
||||
__raw_writel(tgcr, base[i] + TGCR);
|
||||
|
||||
/* Init both counters to zero */
|
||||
__raw_writel(0, base[i] + TIM12);
|
||||
__raw_writel(0, base[i] + TIM34);
|
||||
}
|
||||
|
||||
/* Init of each timer as a 32-bit timer */
|
||||
for (i=0; i< ARRAY_SIZE(timers); i++) {
|
||||
struct timer_s *t = &timers[i];
|
||||
int timer = ID_TO_TIMER(t->id);
|
||||
u32 irq;
|
||||
|
||||
t->base = base[timer];
|
||||
if (!t->base)
|
||||
continue;
|
||||
|
||||
if (IS_TIMER_BOT(t->id)) {
|
||||
t->enamode_shift = 6;
|
||||
t->tim_off = TIM12;
|
||||
t->prd_off = PRD12;
|
||||
irq = dtip[timer].bottom_irq;
|
||||
} else {
|
||||
t->enamode_shift = 22;
|
||||
t->tim_off = TIM34;
|
||||
t->prd_off = PRD34;
|
||||
irq = dtip[timer].top_irq;
|
||||
}
|
||||
|
||||
/* Register interrupt */
|
||||
t->irqaction.name = t->name;
|
||||
t->irqaction.dev_id = (void *)t;
|
||||
|
||||
if (t->irqaction.handler != NULL) {
|
||||
irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
|
||||
setup_irq(irq, &t->irqaction);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* clocksource
|
||||
*/
|
||||
static u64 read_cycles(struct clocksource *cs)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKSOURCE];
|
||||
|
||||
return (cycles_t)timer32_read(t);
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_davinci = {
|
||||
.rating = 300,
|
||||
.read = read_cycles,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
/*
|
||||
* Overwrite weak default sched_clock with something more precise
|
||||
*/
|
||||
static u64 notrace davinci_read_sched_clock(void)
|
||||
{
|
||||
return timer32_read(&timers[TID_CLOCKSOURCE]);
|
||||
}
|
||||
|
||||
/*
|
||||
* clockevent
|
||||
*/
|
||||
static int davinci_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->period = cycles;
|
||||
timer32_config(t);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_shutdown(struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->opts &= ~TIMER_OPTS_STATE_MASK;
|
||||
t->opts |= TIMER_OPTS_DISABLED;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_set_oneshot(struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->opts &= ~TIMER_OPTS_STATE_MASK;
|
||||
t->opts |= TIMER_OPTS_ONESHOT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_set_periodic(struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->period = davinci_clock_tick_rate / (HZ);
|
||||
t->opts &= ~TIMER_OPTS_STATE_MASK;
|
||||
t->opts |= TIMER_OPTS_PERIODIC;
|
||||
timer32_config(t);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clock_event_device clockevent_davinci = {
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC |
|
||||
CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_next_event = davinci_set_next_event,
|
||||
.set_state_shutdown = davinci_shutdown,
|
||||
.set_state_periodic = davinci_set_periodic,
|
||||
.set_state_oneshot = davinci_set_oneshot,
|
||||
};
|
||||
|
||||
void __init davinci_timer_init(struct clk *timer_clk)
|
||||
{
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
unsigned int clockevent_id;
|
||||
unsigned int clocksource_id;
|
||||
int i;
|
||||
|
||||
clockevent_id = soc_info->timer_info->clockevent_id;
|
||||
clocksource_id = soc_info->timer_info->clocksource_id;
|
||||
|
||||
timers[TID_CLOCKEVENT].id = clockevent_id;
|
||||
timers[TID_CLOCKSOURCE].id = clocksource_id;
|
||||
|
||||
/*
|
||||
* If using same timer for both clock events & clocksource,
|
||||
* a compare register must be used to generate an event interrupt.
|
||||
* This is equivalent to a oneshot timer only (not periodic).
|
||||
*/
|
||||
if (clockevent_id == clocksource_id) {
|
||||
struct davinci_timer_instance *dtip =
|
||||
soc_info->timer_info->timers;
|
||||
int event_timer = ID_TO_TIMER(clockevent_id);
|
||||
|
||||
/* Only bottom timers can use compare regs */
|
||||
if (IS_TIMER_TOP(clockevent_id))
|
||||
pr_warn("%s: Invalid use of system timers. Results unpredictable.\n",
|
||||
__func__);
|
||||
else if ((dtip[event_timer].cmp_off == 0)
|
||||
|| (dtip[event_timer].cmp_irq == 0))
|
||||
pr_warn("%s: Invalid timer instance setup. Results unpredictable.\n",
|
||||
__func__);
|
||||
else {
|
||||
timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
|
||||
clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
|
||||
}
|
||||
}
|
||||
|
||||
BUG_ON(IS_ERR(timer_clk));
|
||||
clk_prepare_enable(timer_clk);
|
||||
|
||||
/* init timer hw */
|
||||
timer_init();
|
||||
|
||||
davinci_clock_tick_rate = clk_get_rate(timer_clk);
|
||||
|
||||
/* setup clocksource */
|
||||
clocksource_davinci.name = id_to_name[clocksource_id];
|
||||
if (clocksource_register_hz(&clocksource_davinci,
|
||||
davinci_clock_tick_rate))
|
||||
pr_err("%s: can't register clocksource!\n",
|
||||
clocksource_davinci.name);
|
||||
|
||||
sched_clock_register(davinci_read_sched_clock, 32,
|
||||
davinci_clock_tick_rate);
|
||||
|
||||
/* setup clockevent */
|
||||
clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
|
||||
|
||||
clockevent_davinci.cpumask = cpumask_of(0);
|
||||
clockevents_config_and_register(&clockevent_davinci,
|
||||
davinci_clock_tick_rate, 1, 0xfffffffe);
|
||||
|
||||
for (i=0; i< ARRAY_SIZE(timers); i++)
|
||||
timer32_config(&timers[i]);
|
||||
}
|
||||
@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = {
|
||||
.dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
|
||||
.wkdep_srcs = cam_wkup_sleep_deps,
|
||||
.sleepdep_srcs = cam_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain l4per_7xx_clkdm = {
|
||||
|
||||
@ -653,32 +653,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
|
||||
};
|
||||
|
||||
/* sha0 HIB2 (the 'P' (public) device) */
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
|
||||
.rev_offs = 0x100,
|
||||
.sysc_offs = 0x110,
|
||||
.syss_offs = 0x114,
|
||||
.sysc_flags = SYSS_HAS_RESET_STATUS,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
|
||||
.name = "sham",
|
||||
.sysc = &omap44xx_sha0_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_sha0_hwmod = {
|
||||
.name = "sham",
|
||||
.class = &omap44xx_sha0_hwmod_class,
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.main_clk = "l3_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
@ -727,103 +701,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
Crypto modules AES0/1 belong to:
|
||||
PD_L4_PER power domain
|
||||
CD_L4_SEC clock domain
|
||||
On the L3, the AES modules are mapped to
|
||||
L3_CLK2: Peripherals and multimedia sub clock domain
|
||||
*/
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
|
||||
.rev_offs = 0x80,
|
||||
.sysc_offs = 0x84,
|
||||
.syss_offs = 0x88,
|
||||
.sysc_flags = SYSS_HAS_RESET_STATUS,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
|
||||
.name = "aes",
|
||||
.sysc = &omap44xx_aes_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_aes1_hwmod = {
|
||||
.name = "aes1",
|
||||
.class = &omap44xx_aes_hwmod_class,
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.main_clk = "l3_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
|
||||
.clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_aes1_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_aes2_hwmod = {
|
||||
.name = "aes2",
|
||||
.class = &omap44xx_aes_hwmod_class,
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.main_clk = "l3_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
|
||||
.clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_aes2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'des' class for DES3DES module
|
||||
*/
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
|
||||
.rev_offs = 0x30,
|
||||
.sysc_offs = 0x34,
|
||||
.syss_offs = 0x38,
|
||||
.sysc_flags = SYSS_HAS_RESET_STATUS,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_des_hwmod_class = {
|
||||
.name = "des",
|
||||
.sysc = &omap44xx_des_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_des_hwmod = {
|
||||
.name = "des",
|
||||
.class = &omap44xx_des_hwmod_class,
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.main_clk = "l3_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
|
||||
.clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_des_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/*
|
||||
* 'gpmc' class
|
||||
* general purpose memory controller
|
||||
@ -1735,14 +1612,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> sham */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_sha0_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> gpmc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
@ -1958,10 +1827,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_l4_cfg__usb_tll_hs,
|
||||
&omap44xx_mpu__emif1,
|
||||
&omap44xx_mpu__emif2,
|
||||
&omap44xx_l3_main_2__aes1,
|
||||
&omap44xx_l3_main_2__aes2,
|
||||
&omap44xx_l3_main_2__des,
|
||||
&omap44xx_l3_main_2__sha0,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
@ -604,6 +604,18 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct
|
||||
omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
|
||||
{ OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
|
||||
{ OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "" },
|
||||
{ OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "" },
|
||||
{ OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
|
||||
{ OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "" },
|
||||
{ OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
|
||||
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
|
||||
{ 0 },
|
||||
@ -691,6 +703,7 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
|
||||
{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
|
||||
{ 0x4a009320, omap4_l3_init_clkctrl_regs },
|
||||
{ 0x4a009420, omap4_l4_per_clkctrl_regs },
|
||||
{ 0x4a0095a0, omap4_l4_secure_clkctrl_regs },
|
||||
{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
|
||||
{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
|
||||
{ 0 },
|
||||
|
||||
@ -301,6 +301,18 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct
|
||||
omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "" },
|
||||
{ OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "" },
|
||||
{ OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "" },
|
||||
{ OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "" },
|
||||
{ OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
|
||||
{ OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "" },
|
||||
{ OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
|
||||
{ OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
|
||||
@ -523,6 +535,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
|
||||
{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
|
||||
{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
|
||||
{ 0x4a009020, omap5_l4per_clkctrl_regs },
|
||||
{ 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
|
||||
{ 0x4a009220, omap5_iva_clkctrl_regs },
|
||||
{ 0x4a009420, omap5_dss_clkctrl_regs },
|
||||
{ 0x4a009520, omap5_gpu_clkctrl_regs },
|
||||
|
||||
@ -302,10 +302,6 @@ int __init davinci_timer_register(struct clk *clk,
|
||||
return rv;
|
||||
}
|
||||
|
||||
clockevents_config_and_register(&clockevent->dev, tick_rate,
|
||||
DAVINCI_TIMER_MIN_DELTA,
|
||||
DAVINCI_TIMER_MAX_DELTA);
|
||||
|
||||
davinci_clocksource.dev.rating = 300;
|
||||
davinci_clocksource.dev.read = davinci_clocksource_read;
|
||||
davinci_clocksource.dev.mask =
|
||||
@ -323,6 +319,10 @@ int __init davinci_timer_register(struct clk *clk,
|
||||
davinci_clocksource_init_tim34(base);
|
||||
}
|
||||
|
||||
clockevents_config_and_register(&clockevent->dev, tick_rate,
|
||||
DAVINCI_TIMER_MIN_DELTA,
|
||||
DAVINCI_TIMER_MAX_DELTA);
|
||||
|
||||
rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
|
||||
if (rv) {
|
||||
pr_err("Unable to register clocksource");
|
||||
|
||||
@ -124,6 +124,17 @@
|
||||
#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
|
||||
#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
|
||||
|
||||
/* l4_secure clocks */
|
||||
#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
|
||||
#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
|
||||
#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
|
||||
#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
|
||||
#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
|
||||
#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
|
||||
#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
|
||||
#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
|
||||
#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
|
||||
|
||||
/* l4_wkup clocks */
|
||||
#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
|
||||
|
||||
@ -87,6 +87,17 @@
|
||||
#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
|
||||
#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
|
||||
|
||||
/* l4_secure clocks */
|
||||
#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
|
||||
#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
|
||||
#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
|
||||
#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
|
||||
#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
|
||||
#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
|
||||
#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
|
||||
#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
|
||||
#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
|
||||
|
||||
/* iva clocks */
|
||||
#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user