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coresight: tmc: keep track of memory width
Accessing the HW configuration register each time the memory width is needed simply doesn't make sense. It is much more efficient to read the value once and keep a reference for later use. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -41,25 +41,13 @@ void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
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static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
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{
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enum tmc_mem_intf_width memwidth;
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u8 memwords;
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char *bufp;
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u32 read_data;
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int i;
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memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10);
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if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
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memwords = 1;
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else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
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memwords = 2;
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else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
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memwords = 4;
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else
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memwords = 8;
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bufp = drvdata->buf;
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while (1) {
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for (i = 0; i < memwords; i++) {
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for (i = 0; i < drvdata->memwidth; i++) {
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read_data = readl_relaxed(drvdata->base + TMC_RRD);
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if (read_data == 0xFFFFFFFF)
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return;
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@ -186,6 +186,39 @@ static const struct file_operations tmc_fops = {
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.llseek = no_llseek,
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};
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static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
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{
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enum tmc_mem_intf_width memwidth;
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/*
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* Excerpt from the TRM:
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*
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* DEVID::MEMWIDTH[10:8]
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* 0x2 Memory interface databus is 32 bits wide.
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* 0x3 Memory interface databus is 64 bits wide.
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* 0x4 Memory interface databus is 128 bits wide.
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* 0x5 Memory interface databus is 256 bits wide.
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*/
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switch (BMVAL(devid, 8, 10)) {
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case 0x2:
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memwidth = TMC_MEM_INTF_WIDTH_32BITS;
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break;
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case 0x3:
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memwidth = TMC_MEM_INTF_WIDTH_64BITS;
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break;
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case 0x4:
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memwidth = TMC_MEM_INTF_WIDTH_128BITS;
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break;
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case 0x5:
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memwidth = TMC_MEM_INTF_WIDTH_256BITS;
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break;
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default:
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memwidth = 0;
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}
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return memwidth;
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}
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#define coresight_tmc_simple_func(name, offset) \
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coresight_simple_func(struct tmc_drvdata, name, offset)
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@ -299,6 +332,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
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devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
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drvdata->config_type = BMVAL(devid, 6, 7);
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drvdata->memwidth = tmc_get_memwidth(devid);
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if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
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if (np)
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@ -81,10 +81,10 @@ enum tmc_mode {
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};
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enum tmc_mem_intf_width {
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TMC_MEM_INTF_WIDTH_32BITS = 0x2,
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TMC_MEM_INTF_WIDTH_64BITS = 0x3,
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TMC_MEM_INTF_WIDTH_128BITS = 0x4,
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TMC_MEM_INTF_WIDTH_256BITS = 0x5,
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TMC_MEM_INTF_WIDTH_32BITS = 1,
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TMC_MEM_INTF_WIDTH_64BITS = 2,
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TMC_MEM_INTF_WIDTH_128BITS = 4,
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TMC_MEM_INTF_WIDTH_256BITS = 8,
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};
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/**
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@ -100,6 +100,7 @@ enum tmc_mem_intf_width {
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* @size: @buf size.
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* @mode: how this TMC is being used.
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* @config_type: TMC variant, must be of type @tmc_config_type.
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* @memwidth: width of the memory interface databus, in bytes.
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* @trigger_cntr: amount of words to store after a trigger.
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*/
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struct tmc_drvdata {
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@ -115,6 +116,7 @@ struct tmc_drvdata {
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u32 size;
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local_t mode;
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enum tmc_config_type config_type;
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enum tmc_mem_intf_width memwidth;
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u32 trigger_cntr;
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};
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