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of/pci: Use of_pci_range_parser
This patch converts the pci_load_of_ranges function to use the new common of_pci_range_parser. Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: Andrew Murray <Andrew.Murray@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Andrew Murray
Michal Simek
parent
6e4664525b
commit
4f7b6de437
@ -657,67 +657,42 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
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void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary)
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{
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const u32 *ranges;
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int rlen;
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int pna = of_n_addr_cells(dev);
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int np = pna + 5;
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int memno = 0, isa_hole = -1;
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u32 pci_space;
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unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
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unsigned long long isa_mb = 0;
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struct resource *res;
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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pr_info("PCI host bridge %s %s ranges:\n",
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dev->full_name, primary ? "(primary)" : "");
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/* Get ranges property */
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ranges = of_get_property(dev, "ranges", &rlen);
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if (ranges == NULL)
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/* Check for ranges property */
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if (of_pci_range_parser_init(&parser, dev))
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return;
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/* Parse it */
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pr_debug("Parsing ranges property...\n");
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while ((rlen -= np * 4) >= 0) {
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for_each_of_pci_range(&parser, &range) {
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/* Read next ranges element */
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pci_space = ranges[0];
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pci_addr = of_read_number(ranges + 1, 2);
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cpu_addr = of_translate_address(dev, ranges + 3);
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size = of_read_number(ranges + pna + 3, 2);
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pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
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pci_space, pci_addr);
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range.pci_space, range.pci_addr);
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pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
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cpu_addr, size);
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ranges += np;
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range.cpu_addr, range.size);
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/* If we failed translation or got a zero-sized region
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* (some FW try to feed us with non sensical zero sized regions
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* such as power3 which look like some kind of attempt
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* at exposing the VGA memory hole)
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*/
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if (cpu_addr == OF_BAD_ADDR || size == 0)
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if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
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continue;
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/* Now consume following elements while they are contiguous */
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for (; rlen >= np * sizeof(u32);
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ranges += np, rlen -= np * 4) {
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if (ranges[0] != pci_space)
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break;
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pci_next = of_read_number(ranges + 1, 2);
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cpu_next = of_translate_address(dev, ranges + 3);
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if (pci_next != pci_addr + size ||
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cpu_next != cpu_addr + size)
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break;
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size += of_read_number(ranges + pna + 3, 2);
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}
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/* Act based on address space type */
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res = NULL;
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switch ((pci_space >> 24) & 0x3) {
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case 1: /* PCI IO space */
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switch (range.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
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cpu_addr, cpu_addr + size - 1, pci_addr);
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range.cpu_addr, range.cpu_addr + range.size - 1,
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range.pci_addr);
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/* We support only one IO range */
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if (hose->pci_io_size) {
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@ -725,11 +700,12 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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continue;
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}
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/* On 32 bits, limit I/O space to 16MB */
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if (size > 0x01000000)
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size = 0x01000000;
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if (range.size > 0x01000000)
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range.size = 0x01000000;
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/* 32 bits needs to map IOs here */
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hose->io_base_virt = ioremap(cpu_addr, size);
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hose->io_base_virt = ioremap(range.cpu_addr,
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range.size);
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/* Expect trouble if pci_addr is not 0 */
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if (primary)
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@ -738,19 +714,20 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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/* pci_io_size and io_base_phys always represent IO
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* space starting at 0 so we factor in pci_addr
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*/
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hose->pci_io_size = pci_addr + size;
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hose->io_base_phys = cpu_addr - pci_addr;
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hose->pci_io_size = range.pci_addr + range.size;
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hose->io_base_phys = range.cpu_addr - range.pci_addr;
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/* Build resource */
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res = &hose->io_resource;
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res->flags = IORESOURCE_IO;
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res->start = pci_addr;
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range.cpu_addr = range.pci_addr;
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break;
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case 2: /* PCI Memory space */
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case 3: /* PCI 64 bits Memory space */
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case IORESOURCE_MEM:
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pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
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cpu_addr, cpu_addr + size - 1, pci_addr,
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(pci_space & 0x40000000) ? "Prefetch" : "");
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range.cpu_addr, range.cpu_addr + range.size - 1,
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range.pci_addr,
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(range.pci_space & 0x40000000) ?
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"Prefetch" : "");
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/* We support only 3 memory ranges */
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if (memno >= 3) {
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@ -758,13 +735,13 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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continue;
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}
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/* Handles ISA memory hole space here */
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if (pci_addr == 0) {
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isa_mb = cpu_addr;
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if (range.pci_addr == 0) {
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isa_mb = range.cpu_addr;
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isa_hole = memno;
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if (primary || isa_mem_base == 0)
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isa_mem_base = cpu_addr;
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hose->isa_mem_phys = cpu_addr;
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hose->isa_mem_size = size;
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isa_mem_base = range.cpu_addr;
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hose->isa_mem_phys = range.cpu_addr;
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hose->isa_mem_size = range.size;
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}
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/* We get the PCI/Mem offset from the first range or
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@ -772,30 +749,23 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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* hole. If they don't match, bugger.
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*/
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if (memno == 0 ||
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(isa_hole >= 0 && pci_addr != 0 &&
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(isa_hole >= 0 && range.pci_addr != 0 &&
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hose->pci_mem_offset == isa_mb))
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hose->pci_mem_offset = cpu_addr - pci_addr;
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else if (pci_addr != 0 &&
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hose->pci_mem_offset != cpu_addr - pci_addr) {
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hose->pci_mem_offset = range.cpu_addr -
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range.pci_addr;
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else if (range.pci_addr != 0 &&
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hose->pci_mem_offset != range.cpu_addr -
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range.pci_addr) {
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pr_info(" \\--> Skipped (offset mismatch) !\n");
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continue;
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}
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/* Build resource */
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res = &hose->mem_resources[memno++];
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res->flags = IORESOURCE_MEM;
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if (pci_space & 0x40000000)
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res->flags |= IORESOURCE_PREFETCH;
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res->start = cpu_addr;
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break;
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}
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if (res != NULL) {
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res->name = dev->full_name;
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res->end = res->start + size - 1;
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res->parent = NULL;
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res->sibling = NULL;
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res->child = NULL;
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}
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if (res != NULL)
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of_pci_range_to_resource(&range, dev, res);
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}
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/* If there's an ISA hole and the pci_mem_offset is -not- matching
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