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Merge branch 'drm-dwhdmi-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into drm-next
This set of patches adjust the setup of the HDMI CTS/N values for audio support to be compliant with the work-around given in the iMX6 errata documentation as part of the preparation for integrating audio support for this driver, and also update the HDMI phy configuration for Rockchip devices to improve the HDMI eye pattern. * 'drm-dwhdmi-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: drm: rockchip/dw_hdmi-rockchip: improve for HDMI electrical test drm: bridge/dw_hdmi: separate VLEVCTRL settting into platform driver drm: bridge/dw_hdmi: fixed codec style drm: bridge/dw_hdmi: adjust n/cts setting order drm: bridge/dw_hdmi: protect n/cts setting with a mutex drm: bridge/dw_hdmi: combine hdmi_set_clock_regenerator_n() and hdmi_regenerate_cts() Conflicts: drivers/gpu/drm/imx/dw_hdmi-imx.c
This commit is contained in:
Dave Airlie
commit
52139bdea1
@ -16,6 +16,7 @@
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/hdmi.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <drm/drm_of.h>
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@ -126,6 +127,7 @@ struct dw_hdmi {
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struct i2c_adapter *ddc;
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void __iomem *regs;
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struct mutex audio_mutex;
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unsigned int sample_rate;
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int ratio;
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@ -177,26 +179,23 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
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hdmi_modb(hdmi, data << shift, mask, reg);
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}
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static void hdmi_set_clock_regenerator_n(struct dw_hdmi *hdmi,
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unsigned int value)
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{
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hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
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hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
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hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
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/* nshift factor = 0 */
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hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
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}
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static void hdmi_regenerate_cts(struct dw_hdmi *hdmi, unsigned int cts)
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static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
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unsigned int n)
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{
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/* Must be set/cleared first */
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hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
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hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
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hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
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/* nshift factor = 0 */
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hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
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hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
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HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
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hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
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hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
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hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
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hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
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hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
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}
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static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
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@ -355,18 +354,21 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
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__func__, hdmi->sample_rate, hdmi->ratio,
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pixel_clk, clk_n, clk_cts);
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hdmi_set_clock_regenerator_n(hdmi, clk_n);
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hdmi_regenerate_cts(hdmi, clk_cts);
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hdmi_set_cts_n(hdmi, clk_cts, clk_n);
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}
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static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
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{
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mutex_lock(&hdmi->audio_mutex);
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hdmi_set_clk_regenerator(hdmi, 74250000);
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mutex_unlock(&hdmi->audio_mutex);
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}
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static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
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{
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mutex_lock(&hdmi->audio_mutex);
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hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
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mutex_unlock(&hdmi->audio_mutex);
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}
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/*
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@ -753,10 +755,10 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
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{
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unsigned res_idx, i;
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u8 val, msec;
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const struct dw_hdmi_mpll_config *mpll_config =
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hdmi->plat_data->mpll_cfg;
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const struct dw_hdmi_curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr;
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const struct dw_hdmi_sym_term *sym_term = hdmi->plat_data->sym_term;
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const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
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const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg;
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const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr;
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const struct dw_hdmi_phy_config *phy_config = plat_data->phy_config;
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if (prep)
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return -EINVAL;
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@ -827,18 +829,18 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
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hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
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hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
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for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
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for (i = 0; phy_config[i].mpixelclock != (~0UL); i++)
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if (hdmi->hdmi_data.video_mode.mpixelclock <=
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sym_term[i].mpixelclock)
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phy_config[i].mpixelclock)
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break;
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/* RESISTANCE TERM 133Ohm Cfg */
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hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */
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hdmi_phy_i2c_write(hdmi, phy_config[i].term, 0x19); /* TXTERM */
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/* PREEMP Cgf 0.00 */
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hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
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hdmi_phy_i2c_write(hdmi, phy_config[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
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/* TX/CK LVL 10 */
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hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
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hdmi_phy_i2c_write(hdmi, phy_config[i].vlev_ctr, 0x0E); /* VLEVCTRL */
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/* REMOVE CLK TERM */
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hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
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@ -1569,6 +1571,8 @@ int dw_hdmi_bind(struct device *dev, struct device *master,
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hdmi->ratio = 100;
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hdmi->encoder = encoder;
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mutex_init(&hdmi->audio_mutex);
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of_property_read_u32(np, "reg-io-width", &val);
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switch (val) {
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@ -75,10 +75,10 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
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},
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};
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static const struct dw_hdmi_sym_term imx_sym_term[] = {
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/*pixelclk symbol term*/
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{ 148500000, 0x800d, 0x0005 },
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{ ~0UL, 0x0000, 0x0000 }
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static const struct dw_hdmi_phy_config imx_phy_config[] = {
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/*pixelclk symbol term vlev */
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{ 148500000, 0x800d, 0x0005, 0x01ad},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
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@ -163,7 +163,7 @@ static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con,
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static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
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.mpll_cfg = imx_mpll_cfg,
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.cur_ctr = imx_cur_ctr,
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.sym_term = imx_sym_term,
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.phy_config = imx_phy_config,
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.dev_type = IMX6Q_HDMI,
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.mode_valid = imx6q_hdmi_mode_valid,
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};
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@ -171,7 +171,7 @@ static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
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static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
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.mpll_cfg = imx_mpll_cfg,
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.cur_ctr = imx_cur_ctr,
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.sym_term = imx_sym_term,
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.phy_config = imx_phy_config,
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.dev_type = IMX6DL_HDMI,
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.mode_valid = imx6dl_hdmi_mode_valid,
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};
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@ -133,12 +133,12 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
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}
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};
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static const struct dw_hdmi_sym_term rockchip_sym_term[] = {
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/*pixelclk symbol term*/
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{ 74250000, 0x8009, 0x0004 },
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{ 148500000, 0x8029, 0x0004 },
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{ 297000000, 0x8039, 0x0005 },
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{ ~0UL, 0x0000, 0x0000 }
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static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
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/*pixelclk symbol term vlev*/
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{ 74250000, 0x8009, 0x0004, 0x0272},
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{ 148500000, 0x802b, 0x0004, 0x028d},
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{ 297000000, 0x8039, 0x0005, 0x028d},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
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@ -230,7 +230,7 @@ static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = {
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.mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.sym_term = rockchip_sym_term,
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.phy_config = rockchip_phy_config,
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.dev_type = RK3288_HDMI,
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};
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@ -38,17 +38,18 @@ struct dw_hdmi_curr_ctrl {
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u16 curr[DW_HDMI_RES_MAX];
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};
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struct dw_hdmi_sym_term {
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struct dw_hdmi_phy_config {
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unsigned long mpixelclock;
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u16 sym_ctr; /*clock symbol and transmitter control*/
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u16 term; /*transmission termination value*/
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u16 vlev_ctr; /* voltage level control */
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};
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struct dw_hdmi_plat_data {
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enum dw_hdmi_devtype dev_type;
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const struct dw_hdmi_mpll_config *mpll_cfg;
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const struct dw_hdmi_curr_ctrl *cur_ctr;
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const struct dw_hdmi_sym_term *sym_term;
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const struct dw_hdmi_phy_config *phy_config;
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enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
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struct drm_display_mode *mode);
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};
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