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https://github.com/FEX-Emu/linux.git
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Merge branch 'sh/pci-express-integration'
This commit is contained in:
Paul Mundt
commit
52204705b2
@ -51,6 +51,7 @@ static struct resource sh7786_pci0_resources[] = {
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.name = "PCIe0 MEM 2",
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.start = 0xfe100000,
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.end = 0xfe100000 + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -74,6 +75,7 @@ static struct resource sh7786_pci1_resources[] = {
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.name = "PCIe1 MEM 2",
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.start = 0xfe300000,
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.end = 0xfe300000 + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -82,6 +84,7 @@ static struct resource sh7786_pci2_resources[] = {
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.name = "PCIe2 IO",
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.start = 0xfc800000,
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.end = 0xfc800000 + SZ_4M - 1,
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.flags = IORESOURCE_IO,
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}, {
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.name = "PCIe2 MEM 0",
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.start = 0x80000000,
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@ -96,6 +99,7 @@ static struct resource sh7786_pci2_resources[] = {
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.name = "PCIe2 MEM 2",
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.start = 0xfcd00000,
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.end = 0xfcd00000 + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -204,16 +208,26 @@ static int phy_init(struct pci_channel *chan)
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return -ETIMEDOUT;
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}
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static void pcie_reset(struct sh7786_pcie_port *port)
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{
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struct pci_channel *chan = port->hose;
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pci_write_reg(chan, 1, SH4A_PCIESRSTR);
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pci_write_reg(chan, 0, SH4A_PCIETCTLR);
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pci_write_reg(chan, 0, SH4A_PCIESRSTR);
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pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
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}
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static int pcie_init(struct sh7786_pcie_port *port)
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{
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struct pci_channel *chan = port->hose;
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unsigned int data;
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phys_addr_t memphys;
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size_t memsize;
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int ret, i;
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int ret, i, win;
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/* Begin initialization */
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pci_write_reg(chan, 0, SH4A_PCIETCTLR);
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pcie_reset(port);
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/* Initialize as type1. */
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data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
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@ -327,13 +341,19 @@ static int pcie_init(struct sh7786_pcie_port *port)
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printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
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port->index, (data >> 20) & 0x3f);
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for (i = 0; i < chan->nr_resources; i++) {
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for (i = win = 0; i < chan->nr_resources; i++) {
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struct resource *res = chan->resources + i;
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resource_size_t size;
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u32 enable_mask;
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
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/*
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* We can't use the 32-bit mode windows in legacy 29-bit
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* mode, so just skip them entirely.
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*/
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if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
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continue;
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
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size = resource_size(res);
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@ -342,16 +362,18 @@ static int pcie_init(struct sh7786_pcie_port *port)
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* keeps things pretty simple.
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*/
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__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
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chan->reg_base + SH4A_PCIEPAMR(i));
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chan->reg_base + SH4A_PCIEPAMR(win));
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
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pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
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enable_mask = MASK_PARE;
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if (res->flags & IORESOURCE_IO)
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enable_mask |= MASK_SPC;
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pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
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pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
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win++;
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}
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return 0;
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@ -55,8 +55,11 @@
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#define BITS_ERRRCV (0) /* 0 ERRRCV 0 */
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#define MASK_ERRRCV (1<<BITS_ERRRCV)
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/* PCIEENBLR */
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#define SH4A_PCIEENBLR (0x000008) /* R/W - 0x0000 0001 32 */
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/* PCIEECR */
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#define SH4A_PCIEECR (0x000008) /* R/W - 0x0000 0000 32 */
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#define SH4A_PCIEECR (0x00000C) /* R/W - 0x0000 0000 32 */
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#define BITS_ENBL (0) /* 0 ENBL 0 R/W */
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#define MASK_ENBL (1<<BITS_ENBL)
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@ -113,6 +116,27 @@
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#define BITS_MDATA (0)
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#define MASK_MDATA (0xffffffff<<BITS_MDATA)
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/* PCIEUNLOCKCR */
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#define SH4A_PCIEUNLOCKCR (0x000048) /* R/W - 0x0000 0000 32 */
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/* PCIEIDR */
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#define SH4A_PCIEIDR (0x000060) /* R/W - 0x0101 1101 32 */
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/* PCIEDBGCTLR */
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#define SH4A_PCIEDBGCTLR (0x000100) /* R/W - 0x0000 0000 32 */
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/* PCIEINTXR */
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#define SH4A_PCIEINTXR (0x004000) /* R/W - 0x0000 0000 32 */
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/* PCIERMSGR */
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#define SH4A_PCIERMSGR (0x004010) /* R/W - 0x0000 0000 32 */
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/* PCIERSTR */
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#define SH4A_PCIERSTR(x) (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
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/* PCIESRSTR */
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#define SH4A_PCIESRSTR (0x008040) /* R/W - 0x0000 0000 32 */
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/* PCIEPHYCTLR */
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#define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
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#define BITS_CKE (0)
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@ -121,6 +145,9 @@
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/* PCIERMSGIER */
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#define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */
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/* PCIEPHYCTLR */
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#define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
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/* PCIEPHYADRR */
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#define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */
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#define BITS_ACK (24) // Rev1.171
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@ -152,7 +179,7 @@
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#define MASK_CFINT (1<<BITS_CFINT)
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/* PCIETSTR */
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#define SH4A_PCIETSTR (0x020004) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIETSTR (0x020004) /* R 0x0000 0000 32 */
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/* PCIEINTR */
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#define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */
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@ -236,6 +263,9 @@
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#define BITS_INTPM (8)
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#define MASK_INTPM (1<<BITS_INTPM)
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/* PCIEEH0R */
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#define SH4A_PCIEEHR(x) (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
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/* PCIEAIR */
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#define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */
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@ -244,6 +274,25 @@
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/* PCIEERRFR */ // Rev1.18
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#define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18
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/* PCIEERRFER */
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#define SH4A_PCIEERRFER (0x020024) /* R/W R/W 0x0000 0000 32 */
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/* PCIEERRFR2 */
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#define SH4A_PCIEERRFR2 (0x020028) /* R/W R/W 0x0000 0000 32 */
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/* PCIEMSIR */
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#define SH4A_PCIEMSIR (0x020040) /* R/W - 0x0000 0000 32 */
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/* PCIEMSIFR */
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#define SH4A_PCIEMSIFR (0x020044) /* R/W R/W 0x0000 0000 32 */
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/* PCIEPWRCTLR */
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#define SH4A_PCIEPWRCTLR (0x020100) /* R/W - 0x0000 0000 32 */
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/* PCIEPCCTLR */
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#define SH4A_PCIEPCCTLR (0x020180) /* R/W - 0x0000 0000 32 */
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// Rev1.18
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/* PCIELAR0 */
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#define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */
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@ -352,6 +401,7 @@
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#define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */
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#define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMCHSR0 (0x02112C) /* R/W - 0x0000 0000 32 */
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#define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */
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@ -363,6 +413,7 @@
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#define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */
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#define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMCHSR1 (0x02116C) /* R/W - 0x0000 0000 32 */
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#define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */
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@ -385,6 +436,7 @@
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#define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */
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#define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEDMCHSR3 (0x0211EC) /* R/W R/W 0x0000 0000 32 */
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#define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */
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#define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */
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#define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */
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