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Call efx_set_channels() before efx->type->dimension_resources()
When using the "separate_tx_channels=1" module parameter, the TX queues are initially numbered starting from the first TX-only channel number (after all the RX-only channels). efx_set_channels() renumbers the queues so that they are indexed from zero. On EF10, the TX queues need to be relabelled in this way before calling the dimension_resources NIC type operation, otherwise the TX queue PIO buffers can be linked to the wrong VIs when using "separate_tx_channels=1". Added comments to explain UC/WC mappings for PIO buffers Signed-off-by: Shradha Shah <sshah@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -565,10 +565,17 @@ static int efx_ef10_dimension_resources(struct efx_nic *efx)
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* several of each (in fact that's the only option if host
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* page size is >4K). So we may allocate some extra VIs just
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* for writing PIO buffers through.
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*
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* The UC mapping contains (min_vis - 1) complete VIs and the
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* first half of the next VI. Then the WC mapping begins with
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* the second half of this last VI.
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*/
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uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
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ER_DZ_TX_PIOBUF);
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if (nic_data->n_piobufs) {
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/* pio_write_vi_base rounds down to give the number of complete
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* VIs inside the UC mapping.
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*/
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pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
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wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
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nic_data->n_piobufs) *
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@ -1599,6 +1599,8 @@ static int efx_probe_nic(struct efx_nic *efx)
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if (rc)
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goto fail1;
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efx_set_channels(efx);
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rc = efx->type->dimension_resources(efx);
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if (rc)
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goto fail2;
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@ -1609,7 +1611,6 @@ static int efx_probe_nic(struct efx_nic *efx)
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efx->rx_indir_table[i] =
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ethtool_rxfh_indir_default(i, efx->rss_spread);
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efx_set_channels(efx);
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netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
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netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
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