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[PATCH] PCI Hotplug: shpchp: AMD POGO errata fix
This patch fixes the AMD POGO errata on the hotplug controller where the platform will lock up or reboot if PERR/SERR generation is enabled and a slot is sent an enable command. This fix disables PERR/SERR generation before a slot is sent the enable command by first saving related registers, turning off SERR/PERR generation, enabling the slot, then restoring the registers. Signed-off-by: David Keck <david.keck@amd.com> Cc: Kristen Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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3c0c644188
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53044f3574
drivers/pci/hotplug
@ -95,6 +95,7 @@ struct controller {
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u8 function;
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u8 slot_device_offset;
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u8 add_support;
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u32 pcix_misc2_reg; /* for amd pogo errata */
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enum pci_bus_speed speed;
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u32 first_slot; /* First physical slot number */
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u8 slot_bus; /* Bus where the slots handled by this controller sit */
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@ -113,6 +114,26 @@ struct hotplug_params {
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/* Define AMD SHPC ID */
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#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
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#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
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/* AMD PCIX bridge registers */
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#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
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#define PCIX_MISCII_OFFSET 0x48
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#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
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/* AMD PCIX_MISCII masks and offsets */
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#define PERRNONFATALENABLE_MASK 0x00040000
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#define PERRFATALENABLE_MASK 0x00080000
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#define PERRFLOODENABLE_MASK 0x00100000
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#define SERRNONFATALENABLE_MASK 0x00200000
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#define SERRFATALENABLE_MASK 0x00400000
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/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
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#define PERR_OBSERVED_MASK 0x00000001
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/* AMD PCIX_MEM_BASE_LIMIT masks */
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#define RSE_MASK 0x40000000
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#define INT_BUTTON_IGNORE 0
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#define INT_PRESENCE_ON 1
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@ -333,6 +354,79 @@ static inline int wait_for_ctrl_irq (struct controller *ctrl)
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return retval;
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}
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static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
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{
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u32 pcix_misc2_temp;
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/* save MiscII register */
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pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
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p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
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/* clear SERR/PERR enable bits */
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pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
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pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
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pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
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pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
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pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
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}
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static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
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{
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u32 pcix_misc2_temp;
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u32 pcix_bridge_errors_reg;
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u32 pcix_mem_base_reg;
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u8 perr_set;
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u8 rse_set;
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/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
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pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
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perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
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if (perr_set) {
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dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
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}
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/* write-one-to-clear Memory_Base_Limit[ RSE ] */
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pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
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rse_set = pcix_mem_base_reg & RSE_MASK;
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if (rse_set) {
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dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
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}
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/* restore MiscII register */
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pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
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if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
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pcix_misc2_temp |= SERRFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
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pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
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pcix_misc2_temp |= PERRFLOODENABLE_MASK;
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else
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pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
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pcix_misc2_temp |= PERRFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
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if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
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pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
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else
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pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
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pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
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}
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#define SLOT_NAME_SIZE 10
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static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot)
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@ -894,7 +894,17 @@ int shpchp_enable_slot (struct slot *p_slot)
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dbg("%s: p_slot->pwr_save %x\n", __FUNCTION__, p_slot->pwr_save);
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p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
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rc = board_added(p_slot);
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if(((p_slot->ctrl->pci_dev->vendor == PCI_VENDOR_ID_AMD) ||
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(p_slot->ctrl->pci_dev->device == PCI_DEVICE_ID_AMD_POGO_7458))
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&& p_slot->ctrl->num_slots == 1) {
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/* handle amd pogo errata; this must be done before enable */
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amd_pogo_errata_save_misc_reg(p_slot);
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rc = board_added(p_slot);
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/* handle amd pogo errata; this must be done after enable */
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amd_pogo_errata_restore_misc_reg(p_slot);
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} else
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rc = board_added(p_slot);
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if (rc) {
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p_slot->hpc_ops->get_adapter_status(p_slot,
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&(p_slot->presence_save));
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