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drm/i915: fix per-pipe reads after "cleanup"
In a few places I replaced reads of per-pipe registers with the actual register offsets themselves (converting I915_READ(reg) to _PIPE(reg)). Alexey caught this on his 9xx machine because the cursor control write was affected. A quick audit showed a few more places where I'd borked a read, so here's a patch to fix things up. Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: compilation fix] Tested-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -5220,7 +5220,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
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bool visible = base != 0;
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if (intel_crtc->cursor_visible != visible) {
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uint32_t cntl = CURCNTR(pipe);
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uint32_t cntl = I915_READ(CURCNTR(pipe));
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if (base) {
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cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
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cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
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@ -5590,7 +5590,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 dpll = DPLL(pipe);
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u32 dpll = I915_READ(DPLL(pipe));
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u32 fp;
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intel_clock_t clock;
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@ -5675,13 +5675,14 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
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struct drm_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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struct drm_display_mode *mode;
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int htot = HTOTAL(pipe);
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int hsync = HSYNC(pipe);
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int vtot = VTOTAL(pipe);
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int vsync = VSYNC(pipe);
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int htot = I915_READ(HTOTAL(pipe));
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int hsync = I915_READ(HSYNC(pipe));
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int vtot = I915_READ(VTOTAL(pipe));
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int vsync = I915_READ(VSYNC(pipe));
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mode = kzalloc(sizeof(*mode), GFP_KERNEL);
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if (!mode)
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