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clk: samsung: exynos542x/5800: fix cpu clock configuration data

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Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).

Based on Hardkernel's kernel for ODROID-XU3 board.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz 2015-12-15 18:33:19 +01:00 committed by Sylwester Nawrocki
parent bee4f87f01
commit 54abbdb4ee
1 changed files with 33 additions and 3 deletions
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36
drivers/clk/samsung/clk-exynos5420.c
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@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
{ 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
{ 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
{ 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
{ 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
{ 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 0 },
};
#define E5420_KFC_DIV(kpll, pclk, aclk) \
((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 1300000, E5420_KFC_DIV(3, 5, 2), },
{ 1200000, E5420_KFC_DIV(3, 5, 2), },
{ 1100000, E5420_KFC_DIV(3, 5, 2), },
@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
ARRAY_SIZE(exynos5800_gate_clks));
}
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
if (soc == EXYNOS5420) {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
} else {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
}
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);