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https://github.com/FEX-Emu/linux.git
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USB: xHCI: PCI power management implementation
This patch implements the PCI suspend/resume. Please refer to xHCI spec for doing the suspend/resume operation. For S3, CSS/SRS in USBCMD is used to save/restore the internal state. However, an error maybe occurs while restoring the internal state. In this case, it means that HC internal state is wrong and HC will be re-initialized. Signed-off-by: Libin Yang <libin.yang@amd.com> Signed-off-by: Dong Nguyen <dong.nguyen@amd.com> Signed-off-by: Andiry Xu <andiry.xu@amd.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Andiry Xu
Greg Kroah-Hartman
parent
9777e3ce90
commit
5535b1d5f8
@ -116,6 +116,30 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
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return xhci_pci_reinit(xhci, pdev);
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}
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#ifdef CONFIG_PM
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static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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int retval = 0;
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if (hcd->state != HC_STATE_SUSPENDED)
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return -EINVAL;
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retval = xhci_suspend(xhci);
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return retval;
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}
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static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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int retval = 0;
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retval = xhci_resume(xhci, hibernated);
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return retval;
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}
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#endif /* CONFIG_PM */
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static const struct hc_driver xhci_pci_hc_driver = {
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.description = hcd_name,
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.product_desc = "xHCI Host Controller",
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@ -132,7 +156,10 @@ static const struct hc_driver xhci_pci_hc_driver = {
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*/
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.reset = xhci_pci_setup,
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.start = xhci_run,
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/* suspend and resume implemented later */
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#ifdef CONFIG_PM
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.pci_suspend = xhci_pci_suspend,
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.pci_resume = xhci_pci_resume,
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#endif
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.stop = xhci_stop,
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.shutdown = xhci_shutdown,
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@ -188,6 +215,11 @@ static struct pci_driver xhci_pci_driver = {
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/* suspend and resume implemented later */
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.shutdown = usb_hcd_pci_shutdown,
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#ifdef CONFIG_PM_SLEEP
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.driver = {
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.pm = &usb_hcd_pci_pm_ops
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},
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#endif
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};
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int xhci_register_pci(void)
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@ -551,6 +551,216 @@ void xhci_shutdown(struct usb_hcd *hcd)
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xhci_readl(xhci, &xhci->op_regs->status));
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}
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static void xhci_save_registers(struct xhci_hcd *xhci)
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{
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xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
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xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
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xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
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xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
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xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
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xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
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xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
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xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
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xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
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}
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static void xhci_restore_registers(struct xhci_hcd *xhci)
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{
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xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
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xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
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xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
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xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
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xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
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xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
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xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
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xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
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}
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/*
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* Stop HC (not bus-specific)
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*
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* This is called when the machine transition into S3/S4 mode.
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*
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*/
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int xhci_suspend(struct xhci_hcd *xhci)
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{
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int rc = 0;
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struct usb_hcd *hcd = xhci_to_hcd(xhci);
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u32 command;
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spin_lock_irq(&xhci->lock);
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clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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/* step 1: stop endpoint */
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/* skipped assuming that port suspend has done */
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/* step 2: clear Run/Stop bit */
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command = xhci_readl(xhci, &xhci->op_regs->command);
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command &= ~CMD_RUN;
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xhci_writel(xhci, command, &xhci->op_regs->command);
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if (handshake(xhci, &xhci->op_regs->status,
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STS_HALT, STS_HALT, 100*100)) {
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xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
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spin_unlock_irq(&xhci->lock);
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return -ETIMEDOUT;
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}
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/* step 3: save registers */
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xhci_save_registers(xhci);
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/* step 4: set CSS flag */
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command = xhci_readl(xhci, &xhci->op_regs->command);
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command |= CMD_CSS;
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xhci_writel(xhci, command, &xhci->op_regs->command);
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if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) {
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xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n");
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spin_unlock_irq(&xhci->lock);
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return -ETIMEDOUT;
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}
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/* step 5: remove core well power */
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xhci_cleanup_msix(xhci);
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spin_unlock_irq(&xhci->lock);
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return rc;
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}
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/*
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* start xHC (not bus-specific)
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*
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* This is called when the machine transition from S3/S4 mode.
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*
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*/
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int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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{
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u32 command, temp = 0;
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struct usb_hcd *hcd = xhci_to_hcd(xhci);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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u64 val_64;
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int old_state, retval;
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old_state = hcd->state;
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if (time_before(jiffies, xhci->next_statechange))
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msleep(100);
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spin_lock_irq(&xhci->lock);
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if (!hibernated) {
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/* step 1: restore register */
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xhci_restore_registers(xhci);
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/* step 2: initialize command ring buffer */
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val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
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(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
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xhci->cmd_ring->dequeue) &
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(u64) ~CMD_RING_RSVD_BITS) |
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xhci->cmd_ring->cycle_state;
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xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
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(long unsigned long) val_64);
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xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
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/* step 3: restore state and start state*/
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/* step 3: set CRS flag */
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command = xhci_readl(xhci, &xhci->op_regs->command);
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command |= CMD_CRS;
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xhci_writel(xhci, command, &xhci->op_regs->command);
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if (handshake(xhci, &xhci->op_regs->status,
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STS_RESTORE, 0, 10*100)) {
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xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n");
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spin_unlock_irq(&xhci->lock);
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return -ETIMEDOUT;
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}
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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}
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/* If restore operation fails, re-initialize the HC during resume */
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if ((temp & STS_SRE) || hibernated) {
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usb_root_hub_lost_power(hcd->self.root_hub);
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xhci_dbg(xhci, "Stop HCD\n");
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xhci_halt(xhci);
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xhci_reset(xhci);
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if (hibernated)
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xhci_cleanup_msix(xhci);
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spin_unlock_irq(&xhci->lock);
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#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
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/* Tell the event ring poll function not to reschedule */
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xhci->zombie = 1;
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del_timer_sync(&xhci->event_ring_timer);
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#endif
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xhci_dbg(xhci, "// Disabling event ring interrupts\n");
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
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temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
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xhci_writel(xhci, ER_IRQ_DISABLE(temp),
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&xhci->ir_set->irq_pending);
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xhci_print_ir_set(xhci, xhci->ir_set, 0);
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xhci_dbg(xhci, "cleaning up memory\n");
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xhci_mem_cleanup(xhci);
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xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
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xhci_readl(xhci, &xhci->op_regs->status));
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xhci_dbg(xhci, "Initialize the HCD\n");
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retval = xhci_init(hcd);
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if (retval)
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return retval;
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xhci_dbg(xhci, "Start the HCD\n");
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retval = xhci_run(hcd);
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if (!retval)
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set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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hcd->state = HC_STATE_SUSPENDED;
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return retval;
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}
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/* Re-setup MSI-X */
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if (hcd->irq)
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free_irq(hcd->irq, hcd);
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hcd->irq = -1;
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retval = xhci_setup_msix(xhci);
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if (retval)
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/* fall back to msi*/
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retval = xhci_setup_msi(xhci);
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if (retval) {
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/* fall back to legacy interrupt*/
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retval = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
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hcd->irq_descr, hcd);
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if (retval) {
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xhci_err(xhci, "request interrupt %d failed\n",
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pdev->irq);
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return retval;
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}
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hcd->irq = pdev->irq;
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}
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/* step 4: set Run/Stop bit */
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command = xhci_readl(xhci, &xhci->op_regs->command);
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command |= CMD_RUN;
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xhci_writel(xhci, command, &xhci->op_regs->command);
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handshake(xhci, &xhci->op_regs->status, STS_HALT,
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0, 250 * 1000);
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/* step 5: walk topology and initialize portsc,
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* portpmsc and portli
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*/
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/* this is done in bus_resume */
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/* step 6: restart each of the previously
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* Running endpoints by ringing their doorbells
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*/
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set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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if (!hibernated)
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hcd->state = old_state;
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else
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hcd->state = HC_STATE_SUSPENDED;
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spin_unlock_irq(&xhci->lock);
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return 0;
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}
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/*-------------------------------------------------------------------------*/
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/**
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@ -191,7 +191,7 @@ struct xhci_op_regs {
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/* bits 4:6 are reserved (and should be preserved on writes). */
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/* light reset (port status stays unchanged) - reset completed when this is 0 */
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#define CMD_LRESET (1 << 7)
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/* FIXME: ignoring host controller save/restore state for now. */
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/* host controller save/restore state. */
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#define CMD_CSS (1 << 8)
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#define CMD_CRS (1 << 9)
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/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
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@ -1130,6 +1130,17 @@ struct urb_priv {
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#define XHCI_STOP_EP_CMD_TIMEOUT 5
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/* XXX: Make these module parameters */
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struct s3_save {
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u32 command;
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u32 dev_nt;
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u64 dcbaa_ptr;
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u32 config_reg;
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u32 irq_pending;
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u32 irq_control;
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u32 erst_size;
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u64 erst_base;
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u64 erst_dequeue;
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};
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/* There is one ehci_hci structure per controller */
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struct xhci_hcd {
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@ -1198,6 +1209,7 @@ struct xhci_hcd {
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unsigned long next_statechange;
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u32 command;
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struct s3_save s3;
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/* Host controller is dying - not responding to commands. "I'm not dead yet!"
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*
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* xHC interrupts have been disabled and a watchdog timer will (or has already)
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@ -1393,6 +1405,8 @@ int xhci_init(struct usb_hcd *hcd);
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int xhci_run(struct usb_hcd *hcd);
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void xhci_stop(struct usb_hcd *hcd);
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void xhci_shutdown(struct usb_hcd *hcd);
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int xhci_suspend(struct xhci_hcd *xhci);
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int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
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int xhci_get_frame(struct usb_hcd *hcd);
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irqreturn_t xhci_irq(struct usb_hcd *hcd);
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irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
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