mirror of
https://github.com/FEX-Emu/linux.git
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ARC: intc: split into ARCompact ISA specific, common bits
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
6ffb9c8c5f
commit
5793e273a1
@ -33,6 +33,7 @@
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#define __ASM_ARC_ENTRY_COMPACT_H
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#include <asm/asm-offsets.h>
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#include <asm/irqflags-compact.h>
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#include <asm/thread_info.h> /* For THREAD_SIZE */
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/*--------------------------------------------------------------
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181
arch/arc/include/asm/irqflags-compact.h
Normal file
181
arch/arc/include/asm/irqflags-compact.h
Normal file
@ -0,0 +1,181 @@
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_IRQFLAGS_ARCOMPACT_H
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#define __ASM_IRQFLAGS_ARCOMPACT_H
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/* vineetg: March 2010 : local_irq_save( ) optimisation
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* -Remove explicit mov of current status32 into reg, that is not needed
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* -Use BIC insn instead of INVERTED + AND
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* -Conditionally disable interrupts (if they are not enabled, don't disable)
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*/
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#include <asm/arcregs.h>
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/* status32 Reg bits related to Interrupt Handling */
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#define STATUS_E1_BIT 1 /* Int 1 enable */
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#define STATUS_E2_BIT 2 /* Int 2 enable */
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#define STATUS_A1_BIT 3 /* Int 1 active */
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#define STATUS_A2_BIT 4 /* Int 2 active */
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#define STATUS_E1_MASK (1<<STATUS_E1_BIT)
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#define STATUS_E2_MASK (1<<STATUS_E2_BIT)
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#define STATUS_A1_MASK (1<<STATUS_A1_BIT)
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#define STATUS_A2_MASK (1<<STATUS_A2_BIT)
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#define STATUS_IE_MASK (STATUS_E1_MASK | STATUS_E2_MASK)
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/* Other Interrupt Handling related Aux regs */
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#define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
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#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
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#define AUX_IRQ_LV12 0x43 /* interrupt level register */
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#define AUX_IENABLE 0x40c
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#define AUX_ITRIGGER 0x40d
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#define AUX_IPULSE 0x415
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#ifndef __ASSEMBLY__
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/******************************************************************
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* IRQ Control Macros
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*
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* All of them have "memory" clobber (compiler barrier) which is needed to
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* ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
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* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
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*
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* Noted at the time of Abilis Timer List corruption
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* Orig Bug + Rejected solution : https://lkml.org/lkml/2013/3/29/67
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* Reasoning : https://lkml.org/lkml/2013/4/8/15
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*
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******************************************************************/
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/*
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* Save IRQ state and disable IRQs
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*/
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static inline long arch_local_irq_save(void)
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{
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unsigned long temp, flags;
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__asm__ __volatile__(
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" lr %1, [status32] \n"
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" bic %0, %1, %2 \n"
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" and.f 0, %1, %2 \n"
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" flag.nz %0 \n"
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: "=r"(temp), "=r"(flags)
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: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
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: "memory", "cc");
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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__asm__ __volatile__(
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" flag %0 \n"
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:
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: "r"(flags)
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: "memory");
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}
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/*
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* Unconditionally Enable IRQs
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*/
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extern void arch_local_irq_enable(void);
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/*
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* Unconditionally Disable IRQs
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*/
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static inline void arch_local_irq_disable(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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" and %0, %0, %1 \n"
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" flag %0 \n"
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: "=&r"(temp)
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: "n"(~(STATUS_E1_MASK | STATUS_E2_MASK))
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: "memory");
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}
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/*
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* save IRQ state
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*/
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static inline long arch_local_save_flags(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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: "=&r"(temp)
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:
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: "memory");
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return temp;
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}
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/*
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* Query IRQ state
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*/
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & (STATUS_E1_MASK
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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| STATUS_E2_MASK
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#endif
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));
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#else
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#ifdef CONFIG_TRACE_IRQFLAGS
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.macro TRACE_ASM_IRQ_DISABLE
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bl trace_hardirqs_off
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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bl trace_hardirqs_on
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.endm
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#else
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.macro TRACE_ASM_IRQ_DISABLE
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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.endm
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#endif
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.macro IRQ_DISABLE scratch
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lr \scratch, [status32]
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bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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TRACE_ASM_IRQ_DISABLE
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.endm
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.macro IRQ_ENABLE scratch
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lr \scratch, [status32]
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or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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TRACE_ASM_IRQ_ENABLE
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.endm
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#endif /* __ASSEMBLY__ */
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#endif
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@ -1,4 +1,5 @@
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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@ -9,171 +10,6 @@
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#ifndef __ASM_ARC_IRQFLAGS_H
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#define __ASM_ARC_IRQFLAGS_H
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/* vineetg: March 2010 : local_irq_save( ) optimisation
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* -Remove explicit mov of current status32 into reg, that is not needed
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* -Use BIC insn instead of INVERTED + AND
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* -Conditionally disable interrupts (if they are not enabled, don't disable)
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*/
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#include <asm/arcregs.h>
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/* status32 Reg bits related to Interrupt Handling */
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#define STATUS_E1_BIT 1 /* Int 1 enable */
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#define STATUS_E2_BIT 2 /* Int 2 enable */
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#define STATUS_A1_BIT 3 /* Int 1 active */
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#define STATUS_A2_BIT 4 /* Int 2 active */
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#define STATUS_E1_MASK (1<<STATUS_E1_BIT)
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#define STATUS_E2_MASK (1<<STATUS_E2_BIT)
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#define STATUS_A1_MASK (1<<STATUS_A1_BIT)
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#define STATUS_A2_MASK (1<<STATUS_A2_BIT)
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/* Other Interrupt Handling related Aux regs */
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#define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
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#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
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#define AUX_IRQ_LV12 0x43 /* interrupt level register */
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#define AUX_IENABLE 0x40c
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#define AUX_ITRIGGER 0x40d
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#define AUX_IPULSE 0x415
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#ifndef __ASSEMBLY__
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/******************************************************************
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* IRQ Control Macros
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*
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* All of them have "memory" clobber (compiler barrier) which is needed to
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* ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
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* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
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*
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* Noted at the time of Abilis Timer List corruption
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* Orig Bug + Rejected solution : https://lkml.org/lkml/2013/3/29/67
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* Reasoning : https://lkml.org/lkml/2013/4/8/15
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*
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******************************************************************/
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/*
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* Save IRQ state and disable IRQs
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*/
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static inline long arch_local_irq_save(void)
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{
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unsigned long temp, flags;
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__asm__ __volatile__(
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" lr %1, [status32] \n"
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" bic %0, %1, %2 \n"
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" and.f 0, %1, %2 \n"
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" flag.nz %0 \n"
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: "=r"(temp), "=r"(flags)
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: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
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: "memory", "cc");
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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__asm__ __volatile__(
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" flag %0 \n"
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:
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: "r"(flags)
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: "memory");
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}
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/*
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* Unconditionally Enable IRQs
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*/
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extern void arch_local_irq_enable(void);
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/*
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* Unconditionally Disable IRQs
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*/
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static inline void arch_local_irq_disable(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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" and %0, %0, %1 \n"
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" flag %0 \n"
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: "=&r"(temp)
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: "n"(~(STATUS_E1_MASK | STATUS_E2_MASK))
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: "memory");
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}
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/*
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* save IRQ state
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*/
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static inline long arch_local_save_flags(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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: "=&r"(temp)
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:
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: "memory");
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return temp;
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}
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/*
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* Query IRQ state
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*/
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & (STATUS_E1_MASK
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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| STATUS_E2_MASK
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#endif
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));
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#else
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#ifdef CONFIG_TRACE_IRQFLAGS
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.macro TRACE_ASM_IRQ_DISABLE
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bl trace_hardirqs_off
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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bl trace_hardirqs_on
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.endm
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#else
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.macro TRACE_ASM_IRQ_DISABLE
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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.endm
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#endif
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.macro IRQ_DISABLE scratch
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lr \scratch, [status32]
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bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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TRACE_ASM_IRQ_DISABLE
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.endm
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.macro IRQ_ENABLE scratch
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lr \scratch, [status32]
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or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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TRACE_ASM_IRQ_ENABLE
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.endm
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#endif /* __ASSEMBLY__ */
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#include <asm/irqflags-compact.h>
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#endif
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@ -10,7 +10,7 @@ CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
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obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o process.o devtree.o
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obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o clk.o
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obj-y += entry-compact.o
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obj-y += entry-compact.o intc-compact.o
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obj-$(CONFIG_MODULES) += arcksyms.o module.o
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obj-$(CONFIG_SMP) += smp.o
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226
arch/arc/kernel/intc-compact.c
Normal file
226
arch/arc/kernel/intc-compact.c
Normal file
@ -0,0 +1,226 @@
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/*
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* Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include "../../drivers/irqchip/irqchip.h"
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#include <asm/irq.h>
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/*
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* Early Hardware specific Interrupt setup
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* -Platform independent, needed for each CPU (not foldable into init_IRQ)
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* -Called very early (start_kernel -> setup_arch -> setup_processor)
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*
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* what it does ?
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* -Optionally, setup the High priority Interrupts as Level 2 IRQs
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*/
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void arc_init_IRQ(void)
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{
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int level_mask = 0;
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/* setup any high priority Interrupts (Level2 in ARCompact jargon) */
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level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
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level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
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level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
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/*
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* Write to register, even if no LV2 IRQs configured to reset it
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* in case bootloader had mucked with it
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*/
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write_aux_reg(AUX_IRQ_LEV, level_mask);
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if (level_mask)
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pr_info("Level-2 interrupts bitset %x\n", level_mask);
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}
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/*
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* ARC700 core includes a simple on-chip intc supporting
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* -per IRQ enable/disable
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* -2 levels of interrupts (high/low)
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* -all interrupts being level triggered
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*
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* To reduce platform code, we assume all IRQs directly hooked-up into intc.
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* Platforms with external intc, hence cascaded IRQs, are free to over-ride
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* below, per IRQ.
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*/
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static void arc_irq_mask(struct irq_data *data)
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{
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unsigned int ienb;
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ienb = read_aux_reg(AUX_IENABLE);
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ienb &= ~(1 << data->irq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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static void arc_irq_unmask(struct irq_data *data)
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{
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unsigned int ienb;
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ienb = read_aux_reg(AUX_IENABLE);
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ienb |= (1 << data->irq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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static struct irq_chip onchip_intc = {
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.name = "ARC In-core Intc",
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.irq_mask = arc_irq_mask,
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.irq_unmask = arc_irq_unmask,
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};
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static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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/*
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* XXX: the IPI IRQ needs to be handled like TIMER too. However ARC core
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* code doesn't own it (like TIMER0). ISS IDU / ezchip define it
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* in platform header which can't be included here as it goes
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* against multi-platform image philisophy
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*/
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if (irq == TIMER0_IRQ)
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irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
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else
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irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops arc_intc_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = arc_intc_domain_map,
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};
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static struct irq_domain *root_domain;
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static int __init
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init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
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{
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if (parent)
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panic("DeviceTree incore intc not a root irq controller\n");
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|
||||
root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
|
||||
&arc_intc_domain_ops, NULL);
|
||||
|
||||
if (!root_domain)
|
||||
panic("root irq domain not avail\n");
|
||||
|
||||
/* with this we don't need to export root_domain */
|
||||
irq_set_default_host(root_domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
|
||||
|
||||
/*
|
||||
* arch_local_irq_enable - Enable interrupts.
|
||||
*
|
||||
* 1. Explicitly called to re-enable interrupts
|
||||
* 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
|
||||
* which maybe in hard ISR itself
|
||||
*
|
||||
* Semantics of this function change depending on where it is called from:
|
||||
*
|
||||
* -If called from hard-ISR, it must not invert interrupt priorities
|
||||
* e.g. suppose TIMER is high priority (Level 2) IRQ
|
||||
* Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
|
||||
* Here local_irq_enable( ) shd not re-enable lower priority interrupts
|
||||
* -If called from soft-ISR, it must re-enable all interrupts
|
||||
* soft ISR are low prioity jobs which can be very slow, thus all IRQs
|
||||
* must be enabled while they run.
|
||||
* Now hardware context wise we may still be in L2 ISR (not done rtie)
|
||||
* still we must re-enable both L1 and L2 IRQs
|
||||
* Another twist is prev scenario with flow being
|
||||
* L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
|
||||
* here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
|
||||
* over-written (this is deficiency in ARC700 Interrupt mechanism)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
|
||||
|
||||
void arch_local_irq_enable(void)
|
||||
{
|
||||
|
||||
unsigned long flags = arch_local_save_flags();
|
||||
|
||||
/* Allow both L1 and L2 at the onset */
|
||||
flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
|
||||
|
||||
/* Called from hard ISR (between irq_enter and irq_exit) */
|
||||
if (in_irq()) {
|
||||
|
||||
/* If in L2 ISR, don't re-enable any further IRQs as this can
|
||||
* cause IRQ priorities to get upside down. e.g. it could allow
|
||||
* L1 be taken while in L2 hard ISR which is wrong not only in
|
||||
* theory, it can also cause the dreaded L1-L2-L1 scenario
|
||||
*/
|
||||
if (flags & STATUS_A2_MASK)
|
||||
flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
|
||||
|
||||
/* Even if in L1 ISR, allowe Higher prio L2 IRQs */
|
||||
else if (flags & STATUS_A1_MASK)
|
||||
flags &= ~(STATUS_E1_MASK);
|
||||
}
|
||||
|
||||
/* called from soft IRQ, ideally we want to re-enable all levels */
|
||||
|
||||
else if (in_softirq()) {
|
||||
|
||||
/* However if this is case of L1 interrupted by L2,
|
||||
* re-enabling both may cause whaco L1-L2-L1 scenario
|
||||
* because ARC700 allows level 1 to interrupt an active L2 ISR
|
||||
* Thus we disable both
|
||||
* However some code, executing in soft ISR wants some IRQs
|
||||
* to be enabled so we re-enable L2 only
|
||||
*
|
||||
* How do we determine L1 intr by L2
|
||||
* -A2 is set (means in L2 ISR)
|
||||
* -E1 is set in this ISR's pt_regs->status32 which is
|
||||
* saved copy of status32_l2 when l2 ISR happened
|
||||
*/
|
||||
struct pt_regs *pt = get_irq_regs();
|
||||
|
||||
if ((flags & STATUS_A2_MASK) && pt &&
|
||||
(pt->status32 & STATUS_A1_MASK)) {
|
||||
/*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
|
||||
flags &= ~(STATUS_E1_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
arch_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
#else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
|
||||
|
||||
/*
|
||||
* Simpler version for only 1 level of interrupt
|
||||
* Here we only Worry about Level 1 Bits
|
||||
*/
|
||||
void arch_local_irq_enable(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* ARC IDE Drivers tries to re-enable interrupts from hard-isr
|
||||
* context which is simply wrong
|
||||
*/
|
||||
if (in_irq()) {
|
||||
WARN_ONCE(1, "IRQ enabled from hard-isr");
|
||||
return;
|
||||
}
|
||||
|
||||
flags = arch_local_save_flags();
|
||||
flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
|
||||
arch_local_irq_restore(flags);
|
||||
}
|
||||
#endif
|
||||
EXPORT_SYMBOL(arch_local_irq_enable);
|
||||
@ -8,115 +8,9 @@
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include "../../drivers/irqchip/irqchip.h"
|
||||
#include <asm/sections.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach_desc.h>
|
||||
|
||||
/*
|
||||
* Early Hardware specific Interrupt setup
|
||||
* -Platform independent, needed for each CPU (not foldable into init_IRQ)
|
||||
* -Called very early (start_kernel -> setup_arch -> setup_processor)
|
||||
*
|
||||
* what it does ?
|
||||
* -Optionally, setup the High priority Interrupts as Level 2 IRQs
|
||||
*/
|
||||
void arc_init_IRQ(void)
|
||||
{
|
||||
int level_mask = 0;
|
||||
|
||||
/* setup any high priority Interrupts (Level2 in ARCompact jargon) */
|
||||
level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
|
||||
level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
|
||||
level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
|
||||
|
||||
/*
|
||||
* Write to register, even if no LV2 IRQs configured to reset it
|
||||
* in case bootloader had mucked with it
|
||||
*/
|
||||
write_aux_reg(AUX_IRQ_LEV, level_mask);
|
||||
|
||||
if (level_mask)
|
||||
pr_info("Level-2 interrupts bitset %x\n", level_mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* ARC700 core includes a simple on-chip intc supporting
|
||||
* -per IRQ enable/disable
|
||||
* -2 levels of interrupts (high/low)
|
||||
* -all interrupts being level triggered
|
||||
*
|
||||
* To reduce platform code, we assume all IRQs directly hooked-up into intc.
|
||||
* Platforms with external intc, hence cascaded IRQs, are free to over-ride
|
||||
* below, per IRQ.
|
||||
*/
|
||||
|
||||
static void arc_irq_mask(struct irq_data *data)
|
||||
{
|
||||
unsigned int ienb;
|
||||
|
||||
ienb = read_aux_reg(AUX_IENABLE);
|
||||
ienb &= ~(1 << data->irq);
|
||||
write_aux_reg(AUX_IENABLE, ienb);
|
||||
}
|
||||
|
||||
static void arc_irq_unmask(struct irq_data *data)
|
||||
{
|
||||
unsigned int ienb;
|
||||
|
||||
ienb = read_aux_reg(AUX_IENABLE);
|
||||
ienb |= (1 << data->irq);
|
||||
write_aux_reg(AUX_IENABLE, ienb);
|
||||
}
|
||||
|
||||
static struct irq_chip onchip_intc = {
|
||||
.name = "ARC In-core Intc",
|
||||
.irq_mask = arc_irq_mask,
|
||||
.irq_unmask = arc_irq_unmask,
|
||||
};
|
||||
|
||||
static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
if (irq == TIMER0_IRQ)
|
||||
irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
|
||||
else
|
||||
irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops arc_intc_domain_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.map = arc_intc_domain_map,
|
||||
};
|
||||
|
||||
static struct irq_domain *root_domain;
|
||||
|
||||
static int __init
|
||||
init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
|
||||
{
|
||||
if (parent)
|
||||
panic("DeviceTree incore intc not a root irq controller\n");
|
||||
|
||||
root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
|
||||
&arc_intc_domain_ops, NULL);
|
||||
|
||||
if (!root_domain)
|
||||
panic("root irq domain not avail\n");
|
||||
|
||||
/* with this we don't need to export root_domain */
|
||||
irq_set_default_host(root_domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
|
||||
|
||||
/*
|
||||
* Late Interrupt system init called from start_kernel for Boot CPU only
|
||||
*
|
||||
@ -178,107 +72,3 @@ void arc_request_percpu_irq(int irq, int cpu,
|
||||
|
||||
enable_percpu_irq(irq, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* arch_local_irq_enable - Enable interrupts.
|
||||
*
|
||||
* 1. Explicitly called to re-enable interrupts
|
||||
* 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
|
||||
* which maybe in hard ISR itself
|
||||
*
|
||||
* Semantics of this function change depending on where it is called from:
|
||||
*
|
||||
* -If called from hard-ISR, it must not invert interrupt priorities
|
||||
* e.g. suppose TIMER is high priority (Level 2) IRQ
|
||||
* Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
|
||||
* Here local_irq_enable( ) shd not re-enable lower priority interrupts
|
||||
* -If called from soft-ISR, it must re-enable all interrupts
|
||||
* soft ISR are low prioity jobs which can be very slow, thus all IRQs
|
||||
* must be enabled while they run.
|
||||
* Now hardware context wise we may still be in L2 ISR (not done rtie)
|
||||
* still we must re-enable both L1 and L2 IRQs
|
||||
* Another twist is prev scenario with flow being
|
||||
* L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
|
||||
* here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
|
||||
* over-written (this is deficiency in ARC700 Interrupt mechanism)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
|
||||
|
||||
void arch_local_irq_enable(void)
|
||||
{
|
||||
|
||||
unsigned long flags;
|
||||
flags = arch_local_save_flags();
|
||||
|
||||
/* Allow both L1 and L2 at the onset */
|
||||
flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
|
||||
|
||||
/* Called from hard ISR (between irq_enter and irq_exit) */
|
||||
if (in_irq()) {
|
||||
|
||||
/* If in L2 ISR, don't re-enable any further IRQs as this can
|
||||
* cause IRQ priorities to get upside down. e.g. it could allow
|
||||
* L1 be taken while in L2 hard ISR which is wrong not only in
|
||||
* theory, it can also cause the dreaded L1-L2-L1 scenario
|
||||
*/
|
||||
if (flags & STATUS_A2_MASK)
|
||||
flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
|
||||
|
||||
/* Even if in L1 ISR, allowe Higher prio L2 IRQs */
|
||||
else if (flags & STATUS_A1_MASK)
|
||||
flags &= ~(STATUS_E1_MASK);
|
||||
}
|
||||
|
||||
/* called from soft IRQ, ideally we want to re-enable all levels */
|
||||
|
||||
else if (in_softirq()) {
|
||||
|
||||
/* However if this is case of L1 interrupted by L2,
|
||||
* re-enabling both may cause whaco L1-L2-L1 scenario
|
||||
* because ARC700 allows level 1 to interrupt an active L2 ISR
|
||||
* Thus we disable both
|
||||
* However some code, executing in soft ISR wants some IRQs
|
||||
* to be enabled so we re-enable L2 only
|
||||
*
|
||||
* How do we determine L1 intr by L2
|
||||
* -A2 is set (means in L2 ISR)
|
||||
* -E1 is set in this ISR's pt_regs->status32 which is
|
||||
* saved copy of status32_l2 when l2 ISR happened
|
||||
*/
|
||||
struct pt_regs *pt = get_irq_regs();
|
||||
if ((flags & STATUS_A2_MASK) && pt &&
|
||||
(pt->status32 & STATUS_A1_MASK)) {
|
||||
/*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
|
||||
flags &= ~(STATUS_E1_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
arch_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
#else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
|
||||
|
||||
/*
|
||||
* Simpler version for only 1 level of interrupt
|
||||
* Here we only Worry about Level 1 Bits
|
||||
*/
|
||||
void arch_local_irq_enable(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* ARC IDE Drivers tries to re-enable interrupts from hard-isr
|
||||
* context which is simply wrong
|
||||
*/
|
||||
if (in_irq()) {
|
||||
WARN_ONCE(1, "IRQ enabled from hard-isr");
|
||||
return;
|
||||
}
|
||||
|
||||
flags = arch_local_save_flags();
|
||||
flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
|
||||
arch_local_irq_restore(flags);
|
||||
}
|
||||
#endif
|
||||
EXPORT_SYMBOL(arch_local_irq_enable);
|
||||
|
||||
@ -166,8 +166,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
|
||||
* [L] ZOL loop inhibited to begin with - cleared by a LP insn
|
||||
* Interrupts enabled
|
||||
*/
|
||||
regs->status32 = STATUS_U_MASK | STATUS_L_MASK |
|
||||
STATUS_E1_MASK | STATUS_E2_MASK;
|
||||
regs->status32 = STATUS_U_MASK | STATUS_L_MASK | STATUS_IE_MASK;
|
||||
|
||||
/* bogus seed values for debugging */
|
||||
regs->lp_start = 0x10;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user