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parisc: Clean up linker script using new linker script macros.

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This patch has the (likely harmless) side effect of moving
.data.init_task inside the _edata.

It also changes the alignment of .data.init_task from 16384 to
THREAD_SIZE, which can in some configurations be larger than 16384.  I
believe that this change fixes a potential bug on those
configurations.

Signed-off-by: Tim Abbott <tabbott@ksplice.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Helge Deller <deller@gmx.de>
Cc: linux-parisc@vger.kernel.org
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Tim Abbott 2009-09-24 10:36:17 -04:00 committed by Linus Torvalds
parent 1b2086227c
commit 57a8e1161e
1 changed files with 4 additions and 75 deletions
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79
arch/parisc/kernel/vmlinux.lds.S
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@ -77,13 +77,7 @@ SECTIONS
*/ */
. = ALIGN(PAGE_SIZE); . = ALIGN(PAGE_SIZE);
data_start = .; data_start = .;
. = ALIGN(16); EXCEPTION_TABLE(16)
/* Exception table */
__ex_table : {
__start___ex_table = .;
*(__ex_table)
__stop___ex_table = .;
}
NOTES NOTES
@ -94,23 +88,8 @@ SECTIONS
__stop___unwind = .; __stop___unwind = .;
} }
/* rarely changed data like cpu maps */
. = ALIGN(16);
.data.read_mostly : {
*(.data.read_mostly)
}
. = ALIGN(L1_CACHE_BYTES);
/* Data */ /* Data */
.data : { RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
DATA_DATA
CONSTRUCTORS
}
. = ALIGN(L1_CACHE_BYTES);
.data.cacheline_aligned : {
*(.data.cacheline_aligned)
}
/* PA-RISC locks requires 16-byte alignment */ /* PA-RISC locks requires 16-byte alignment */
. = ALIGN(16); . = ALIGN(16);
@ -118,17 +97,6 @@ SECTIONS
*(.data.lock_aligned) *(.data.lock_aligned)
} }
/* nosave data is really only used for software suspend...it's here
* just in case we ever implement it
*/
. = ALIGN(PAGE_SIZE);
__nosave_begin = .;
.data_nosave : {
*(.data.nosave)
}
. = ALIGN(PAGE_SIZE);
__nosave_end = .;
/* End of data section */ /* End of data section */
_edata = .; _edata = .;
@ -147,14 +115,6 @@ SECTIONS
} }
__bss_stop = .; __bss_stop = .;
/* assembler code expects init_task to be 16k aligned */
. = ALIGN(16384);
/* init_task */
.data.init_task : {
*(.data.init_task)
}
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
. = ALIGN(16); . = ALIGN(16);
/* Linkage tables */ /* Linkage tables */
@ -172,31 +132,8 @@ SECTIONS
/* reserve space for interrupt stack by aligning __init* to 16k */ /* reserve space for interrupt stack by aligning __init* to 16k */
. = ALIGN(16384); . = ALIGN(16384);
__init_begin = .; __init_begin = .;
.init.text : { INIT_TEXT_SECTION(16384)
_sinittext = .; INIT_DATA_SECTION(16)
INIT_TEXT
_einittext = .;
}
.init.data : {
INIT_DATA
}
. = ALIGN(16);
.init.setup : {
__setup_start = .;
*(.init.setup)
__setup_end = .;
}
.initcall.init : {
__initcall_start = .;
INITCALLS
__initcall_end = .;
}
.con_initcall.init : {
__con_initcall_start = .;
*(.con_initcall.init)
__con_initcall_end = .;
}
SECURITY_INIT
/* alternate instruction replacement. This is a mechanism x86 uses /* alternate instruction replacement. This is a mechanism x86 uses
* to detect the CPU type and replace generic instruction sequences * to detect the CPU type and replace generic instruction sequences
@ -222,14 +159,6 @@ SECTIONS
.exit.data : { .exit.data : {
EXIT_DATA EXIT_DATA
} }
#ifdef CONFIG_BLK_DEV_INITRD
. = ALIGN(PAGE_SIZE);
.init.ramfs : {
__initramfs_start = .;
*(.init.ramfs)
__initramfs_end = .;
}
#endif
PERCPU(PAGE_SIZE) PERCPU(PAGE_SIZE)
. = ALIGN(PAGE_SIZE); . = ALIGN(PAGE_SIZE);