FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2025-01-16 06:31:46 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/i915/vlv: split CCK and DDR freq usage

Browse Source 
It's possible that the CCK clock could run at a different rate than the
DDR clock, so use the same method to get CCK as the GMBUS code does when
calculating the new CDclk divider in the VLV display code.

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes 2013-11-04 16:06:59 -08:00 committed by Daniel Vetter
parent 30a970c6a6
commit 586f49dc78
3 changed files with 12 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/gpu/drm/i915/intel_display.c
View File

@ -3894,24 +3894,17 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
static int valleyview_get_vco(struct drm_i915_private *dev_priv)
int valleyview_get_vco(struct drm_i915_private *dev_priv)
{
int vco;
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
switch (dev_priv->mem_freq) {
default:
case 800:
vco = 800;
break;
case 1066:
vco = 1600;
break;
case 1333:
vco = 2000;
break;
}
/* Obtain SKU information */
mutex_lock(&dev_priv->dpio_lock);
hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK;
mutex_unlock(&dev_priv->dpio_lock);
return vco;
return vco_freq[hpll_freq];
}
/* Adjust CDclk dividers to allow high res or save power if possible */

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -693,7 +693,7 @@ void i915_disable_vga_mem(struct drm_device *dev);
void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);

11
drivers/gpu/drm/i915/intel_i2c.c
View File

@ -82,16 +82,11 @@ static int get_disp_clk_div(struct drm_i915_private *dev_priv,
static void gmbus_set_freq(struct drm_i915_private *dev_priv)
{
int vco_freq[] = { 800, 1600, 2000, 2400 };
int gmbus_freq = 0, cdclk_div, hpll_freq;
int vco, gmbus_freq = 0, cdclk_div;
BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
/* Obtain SKU information */
mutex_lock(&dev_priv->dpio_lock);
hpll_freq =
vlv_cck_read(dev_priv, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK;
mutex_unlock(&dev_priv->dpio_lock);
vco = valleyview_get_vco(dev_priv);
/* Get the CDCLK divide ratio */
cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
@ -102,7 +97,7 @@ static void gmbus_set_freq(struct drm_i915_private *dev_priv)
* in fact 1MHz is the correct frequency.
*/
if (cdclk_div)
gmbus_freq = (vco_freq[hpll_freq] << 1) / cdclk_div;
gmbus_freq = (vco << 1) / cdclk_div;
if (WARN_ON(gmbus_freq == 0))
return;