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PCI: Always set prefetchable base/limit upper32 registers
Prior to1f82de10
we always initialized the upper 32bits of the prefetchable memory window, regardless of the address range used. Now we only touch it for a >32bit address, which means the upper32 registers remain whatever the BIOS initialized them too. It's valid for the BIOS to set the upper32 base/limit to 0xffffffff/0x00000000, which makes us program prefetchable ranges like 0xffffffffabc00000 - 0x00000000abc00000 Revert the chunk of1f82de10
that made this conditional so we always write the upper32 registers and remove now unused pref_mem64 variable. Signed-off-by: Alex Williamson <alex.williamson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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@ -140,7 +140,6 @@ static void pci_setup_bridge(struct pci_bus *bus)
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struct resource *res;
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struct pci_bus_region region;
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u32 l, bu, lu, io_upper16;
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int pref_mem64;
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if (pci_is_enabled(bridge))
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return;
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@ -194,7 +193,6 @@ static void pci_setup_bridge(struct pci_bus *bus)
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pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
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/* Set up PREF base/limit. */
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pref_mem64 = 0;
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bu = lu = 0;
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res = bus->resource[2];
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pcibios_resource_to_bus(bridge, ®ion, res);
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@ -202,7 +200,6 @@ static void pci_setup_bridge(struct pci_bus *bus)
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l = (region.start >> 16) & 0xfff0;
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l |= region.end & 0xfff00000;
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if (res->flags & IORESOURCE_MEM_64) {
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pref_mem64 = 1;
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bu = upper_32_bits(region.start);
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lu = upper_32_bits(region.end);
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}
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@ -214,11 +211,9 @@ static void pci_setup_bridge(struct pci_bus *bus)
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}
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
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if (pref_mem64) {
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/* Set the upper 32 bits of PREF base & limit. */
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
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pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
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}
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/* Set the upper 32 bits of PREF base & limit. */
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
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pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
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pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
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}
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